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7542 Group
"00"
"01"
"11"
Clock
Frequency
division ratio
divider
selection bits
X
1/16
IN
1/2
On-chip
1/1
"10"
oscillator
CPU mode register
CNTR
edge switch bit
P1
/CNTR
4
0
Port P1
direction
4
register
Pulse output mode
P0
/TX
3
OUT
Port P0
P0
/TX
output valid
3
OUT
Port P0
3
direction
register
Fig. 28 Block diagram of timer 1 and timer X
Rev.3.02
Oct 31, 2006
REJ03B0006-0302
Prescaler 1 latch (8)
Prescaler 1 (8)
1/16
Timer X count
source selection bits
Pulse width
Timer mode
measurement
Pulse output mode
mode
active
0
Event
Timer X count stop bit
counter
"0"
"0"
mode
"1"
CNTR
active
0
edge switch bit
Port P1
4
latch
latch
3
Page 32 of 134
Data bus
Timer 1 latch (8)
Timer 1 (8)
Data bus
Prescaler X latch (8)
Prescaler X (8)
"1"
Q
T
Toggle flip-flop
Q
R
"0"
Timer 1 interrupt
request
Timer X latch (8)
Timer X
Timer X (8)
interrupt
request bit
CNTR
interrupt
request bit
Writing to timer X latch
Pulse output mode
0
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