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7542 Group
Serial I/O2
Serial I/O2 can be used as either clock synchronous or asynchro-
nous (UART) serial I/O. A dedicated timer is also provided for
baud rate generation.
P 0
/ R
D
4
X
2
P 0
/ S
6
C L K 2
B R G c o u n t s o u r c e s e l e c t i o n b i t
X
I N
P 0
/ S
7
R D Y 2
F / F
P 0
/ T
D
5
X
2
Fig. 60 Block diagram of clock synchronous serial I/O2
Transfer shift clock
(1/2 to 1/2048 of the internal
clock, or an external clock)
Serial output TxD
Serial input RxD
Receive enable signal S
RDY2
Write pulse to receive/transmit
buffer register 2 (address 002E
Notes 1: As the transmit interrupt (TI), which can be selected, either when the transmit buffer has emptied (TBE=1) or after
the transmit shift operation has ended (TSC=1), by setting the transmit interrupt source selection bit (TIC) of the
serial I/O2 control register.
2: If data is written to the transmit buffer register when TSC=0, the transmit clock is generated continuously and serial
data is output continuously from the TxD
3: The receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes "1" .
Fig. 61 Operation of clock synchronous serial I/O2 function
Rev.3.02
Oct 31, 2006
REJ03B0006-0302
D a t a b u s
R e c e i v e b u f f e r r e g i s t e r 2
R e c e i v e s h i f t r e g i s t e r 2
1 / 4
F a l l i n g - e d g e d e t e c t o r
T r a n s m i t s h i f t r e g i s t e r 2
T r a n s m i t b u f f e r r e g i s t e r 2
D a t a b u s
2
D
0
D
2
0
)
16
TBE = 0
TBE = 1
TSC = 0
pin.
2
Page 51 of 134
(1) Clock Synchronous Serial I/O2 Mode
Clock synchronous serial I/O2 mode can be selected by setting
the serial I/O2 mode selection bit of the serial I/O2 control register
(bit 6) to "1".
For clock synchronous serial I/O2, the transmitter and the receiver
must use the same clock. If an internal clock is used, transfer is
started by a write signal to the TB/RB.
S e r i a l I / O 2 c o n t r o l r e g i s t e r
A d d r e s s 0 0 2 E
1 6
S h i f t c l o c k
C l o c k c o n t r o l c i r c u i t
S e r i a l I / O 2 s y n c h r o n o u s
c l o c k s e l e c t i o n b i t
F r e q u e n c y d i v i s i o n r a t i o 1 / ( n + 1 )
B a u d r a t e g e n e r a t o r 2
A d d r e s s 0 0 3 2
1 6
C l o c k c o n t r o l c i r c u i t
S h i f t c l o c k
T r a n s m i t i n t e r r u p t s o u r c e s e l e c t i o n b i t
A d d r e s s 0 0 2 E
1 6
D
D
D
1
2
3
D
D
D
1
2
3
A d d r e s s 0 0 3 0
R e c e i v e b u f f e r f u l l f l a g ( R B F )
R e c e i v e i n t e r r u p t r e q u e s t ( R I )
1 / 4
T r a n s m i t s h i f t c o m p l e t i o n f l a g ( T S C )
T r a n s m i t i n t e r r u p t r e q u e s t ( T I )
T r a n s m i t b u f f e r e m p t y f l a g ( T B E )
S e r i a l I / O 2 s t a t u s r e g i s t e r
D
D
D
4
5
6
D
D
D
4
5
6
Overrun error (OE)
detection
1 6
A d d r e s s 0 0 2 F
1 6
D
7
D
7
RBF = 1
TSC = 1
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