Advertisement
7542 Group
f(X
) oscillation: enabled
IN
On-chip oscillator: stop
WAIT mode 1
Interrupt
WIT
instruction
State 1
Operation clock source: f(X
Notes on switch of clock
(1) In operation clock = f(X
f(X
)/2 (high-speed mode)
IN
f(X
)/8 (middle-speed mode)
IN
f(X
) (double-speed mode, only at a ceramic oscillation)
IN
(2) In operation clock = On-chip oscillator, the following can be selected for the CPU clock division ratio.
R
/1 (On-chip oscillator double-speed mode)
OSC
R
/2 (On-chip oscillator high-speed mode)
OSC
R
/8 (On-chip oscillator middle-speed mode)
OSC
R
/128 (On-chip oscillator low-speed mode)
OSC
(3) After system is released from reset, and state transition of state 2 → state 3 and state transition of state 2' → state 3',
R
/8 (On-chip oscillator middle-speed mode) is selected for CPU clock.
OSC
(4) Executing the state transition state 3 to 2 or state 3 to 3' after stabilizing X
(5) When the state 2 → state 3 → state 4 is performed, execute the NOP instruction as shown below
according to the division ratio of CPU clock.
1. CPUM
= 10
(state 2 → state 3)
76
2
2. NOP instruction
Transition from Double-speed mode: NOP
Transition from High-speed mode: NOP
Transition from Middle-speed mode: NOP
3. CPU
= 1
(state 3 → state 4)
4
2
(6) When the state 3 → state 2 → state 1 is performed, execute the NOP instruction as shown below
according to the division ratio of CPU clock.
1. CPUM
= 00
or 01
76
2
2. NOP instruction
Transition from On-chip oscillator double-speed mode: NOP
Transition from On-chip oscillator high-speed mode: NOP
Transition from On-chip oscillator middle-speed mode: NOP
Transition from On-chip oscillator low-speed mode: NOP
3. CPUM
= 1
(state 2 → state 1)
3
2
Fig. 81 State transition
Rev.3.02
Oct 31, 2006
REJ03B0006-0302
Interrupt
STP
Interrupt
instruction
f(X
) oscillation: enabled
IN
On-chip oscillator: enabled
WAIT mode 2
WIT
Interrupt
instruction
CPUM
=0
3
2
State 2
CPUM
=1
3
2
MISRG
=1
MISRG
=0
1
2
1
2
State 2'
WIT
Interrupt
instruction
WAIT mode 2'
f(X
) oscillation: enabled
IN
On-chip oscillator: enabled
Oscillation stop detection circuit valid
) (Note 1)
IN
), the following can be selected for the CPU clock division ratio.
IN
3
1
0
or 11
(state 3 → state 2)
2
2
Page 64 of 134
STP mode
f(X
) oscillation: stop
IN
On-chip oscillator: stop
STP
Interrupt
instruction
Interrupt
f(X
) oscillation: enabled
IN
On-chip oscillator: enabled
STP
instruction
WAIT mode 3
WIT
Interrupt
instruction
CPUM
=10
76
2
(Note 3)
State 3
CPUM
=00
76
2
01
2
11
2
(Note 4)
MISRG
=1
1
2
MISRG
(Note 4)
CPUM
=10
76
2
(Note 3)
State 3'
CPUM
=00
76
2
01
2
11
2
WIT
Interrupt
instruction
WAIT mode 3'
f(X
) oscillation: enabled
IN
On-chip oscillator: enabled
Operation clock source: On-chip oscillator (Note 2)
oscillation.
IN
4
2
0
0
STP
instruction
f(X
) oscillation: stop
IN
On-chip oscillator: enabled
WAIT mode 4
WIT
Interrupt
instruction
CPUM
=0
4
2
State 4
CPUM
=1
4
2
Reset
=0
1
2
released
(Note 3)
RESET state
f(X
) oscillation: enabled
IN
On-chip oscillator: enabled
Advertisement
