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7542 Group
3. Interrupt discrimination bit
Use an LDM instruction to clear to "0" an interrupt discrimination
bit.
LDM #%0000XXXX, $0B
Set the following values to "X"
"0": an interrupt discrimination bit to clear
"1": other interrupt discrimination bits
Ex.) When a key-on wakeup interrupt discrimination bit is cleared;
LDM #%00001110 and $0B.
4. Interrupt discrimination bit and interrupt request bit
For key-on wakeup, UART1 bus collision detection, A/D conver-
sion and Timer 1 interrupt, even if each interrupt valid bit (interrupt
source set register (address 0A
rupt discrimination bit (interrupt source discrimination register
(address 0B
)) is set to "1: interrupt occurs" when corresponding
16
interrupt request occurs.
But corresponding interrupt request bit (interrupt request registers
1, 2 (addresses 3C
, 3D
) is not affected.
16
16
Rev.3.02
Oct 31, 2006
REJ03B0006-0302
)) is set "0: Invalid", each inter-
16
Page 128 of 134
Notes on Timers
1. When n (0 to 255) is written to a timer latch, the frequency divi-
sion ratio is 1/(n+1).
2. When a count source of timer X, timer A or timer B is switched,
stop a count of the timer.
Notes on Timer X
1. CNTR
interrupt active edge selection
0
CNTR
interrupt active edge depends on the CNTR
0
switch bit (bit 2 of timer X mode register (address 2B
When this bit is "0", the CNTR
the falling edge of CNTR
pin input signal. When this bit is "1", the
0
CNTR
interrupt request bit is set to "1" at the rising edge of
0
CNTR
pin input signal.
0
2. Timer X count source selection
The f(X
) (frequency not divided) can be selected by the timer X
IN
count source selection bits (bits 1 and 0 of timer count source set
register (address 2A
)) only when the ceramic oscillation or the
16
on-chip oscillator is selected.
Do not select it for the timer X count source at the RC oscillation.
3. Pulse output mode
Set the direction register of port P1
pin, to output.
When the TX
pin is used, set the direction register of port P0
OUT
which is also used as TX
OUT
4. Pulse width measurement mode
Set the direction register of port P1
pin, to input.
Notes on Timer A, B
1. Setting of timer value
When "1: Write to only latch" is set to the timer A (B) write control
bit (bit 0 (bit 2) of timer X mode register (address 1D
data to timer register is set to only latch even if timer is stopped or
operating. Accordingly, in order to set the initial value for timer
when it is stopped, set "0: Write to latch and timer simultaneously"
to timer A (B) write control bit.
2. Read/write of timer A
Stop timer A to read/write its data in the following state;
X
oscillation selected by clock division ratio selection bits (bits 7
IN
and 6 of CPU mode register (address 3B
cillator output is selected as the timer A count source.
3. Read/write of timer B
Stop timer B to read/write its data in the following state;
X
oscillation selected by clock division ratio selection bits, the
IN
timer A underflow is selected as the timer B count source, and the
on-chip oscillator output is selected as the timer A count source.
active edge
0
)).
16
interrupt request bit is set to "1" at
0
, which is also used as CNTR
4
pin, to output.
, which is also used as CNTR
4
)), written
16
)), and the on-chip os-
16
0
,
3
0
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