Advertisement
7542 Group
Bus collision detection (SIO1)
SIO1 can detect a bus collision by setting UART1 bus collision de-
tection interrupt enable bit.
When transmission is started in the clock synchronous or asyn-
chronous (UART) serial I/O mode, the transmit pin TxD
compared with the receive pin RxD
edge of transmit shift clock. If they do not coincide with each other,
a bus collision detection interrupt request occurs.
When a transmit data collision is detected between LSB and MSB
of transmit data in the clock synchronous serial I/O mode or be-
tween the start bit and stop bit of transmit data in UART mode, a
bus collision detection can be performed by both the internal clock
and the external clock.
A block diagram is shown in Fig. 58.
A timing diagram is shown in Fig. 59.
Note: Bus collision detection can be used when SIO1 is operating
at full-duplex communication. When SIO1 is operating at
half-duplex communication, set bus collision detection inter-
rupt to be disabled.
UART1 bus collision detection
Fig. 58 Block diagram of bus collision detection interrupt circuit
Fig. 59 Timing diagram of bus collision detection interrupt
Rev.3.02
Oct 31, 2006
REJ03B0006-0302
in synchronization with rising
1
TxD
1
RxD
1
Shift clock
interrupt valid bit
(Address 000A
, bit 1)
16
Transmit shift clock
Transmit pin TxD
1
Receive pin RxD
1
Page 50 of 134
b7
is
1
b7
b7
b7
Fig. 57 Bus collision detection circuit related registers
UART1 bus collision detection
interrupt discrimination bit
(Address 000B
D
Q
Key-on wakeup/
UART1 bus collision detection
interrupt request bit
(Address 003C
Key-on wakeup interrupt request
Data collision
b0
Interrupt source set register
(INTSET: address 000A
, initial value: 00
16
Key-on wakeup interrupt valid bit
UART1 bus collision detection
interrupt valid bit
A/D conversion interrupt valid bit
Timer 1 interrupt valid bit
Not used (returns "0" when read)
0: Interrupt invalid
1: Interrupt valid
b0
Interrupt source discrimination register
(INTDIS: address 000B
, initial value: 00
16
Key-on wakeup interrupt discrimination bit
UART1 bus collision detection interrupt
discrimination bit
A/D conversion interrupt discrimination bit
Timer 1 interrupt discrimination bit
Not used (returns "0" when read)
0: Interrupt does not occur
1: Interrupt occurs
b0
Interrupt request register 1
(IREQ1 : address 003C
, initial value : 00
16
Serial I/O1 receive interrupt request bit
Serial I/O1 transmit interrupt request bit
Serial I/O2 receive interrupt request bit
Serial I/O2 transmit interrupt request bit
INT
interrupt request bit
0
INT
interrupt request bit
1
Key-on wake up/UART1 bus collision
detection interrupt request bit
CNTR
interrupt request bit
0
0 : No interrupt request issued
1 : Interrupt request issued
b0
Interrupt control register 1
(ICON1 : address 003E
, initial value : 00
16
Serial I/O1 receive interrupt enable bit
Serial I/O1 transmit interrupt enable bit
Serial I/O2 receive interrupt enable bit
Serial I/O2 transmit interrupt enable bit
INT
interrupt enable bit
0
INT
interrupt enable bit
1
Key-on wake up/UART1 bus collision
detection interrupt enable bit
CNTR
interrupt enable bit
0
0 : Interrupts disabled
1 : Interrupts enabled
, bit 1)
16
, bit 6)
16
Bus collision detection
interrupt generation
)
16
)
16
)
16
)
16
Advertisement
