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Table 8 Interrupt vector address and priority
Interrupt source
Priority
Reset (Note 2)
1
Serial I/O1 receive
2
Serial I/O1 transmit
3
Serial I/O2 receive
4
Serial I/O2 transmit
5
INT
6
0
INT
7
1
Key-on wake-up/
8
UART1 bus
collision detection
(Note 3)
CNTR
9
0
Capture 0
10
Capture 1
11
Compare
12
Timer X
13
Timer A
14
Timer B
15
A/D conversion/
16
Timer 1
(Note 4)
BRK instruction
17
Note 1: Vector addressed contain internal jump destination addresses.
2: Reset function in the same way as an interrupt with the highest priority.
3: Key-on wakeup interrupt and UART1 bus collision detection interrupt can be enabled by setting of interrupt source set register. The occurrence of
these interrupts are discriminated by interrupt source discrimination register.
4: A/D conversion interrupt and Timer 1 interrupt can be enabled by setting of interrupt source set register. The occurrence of these interrupts are dis-
criminated by interrupt source discrimination register.
Rev.3.02
Oct 31, 2006
REJ03B0006-0302
Vector addresses (Note 1)
High-order
Low-order
FFFD
FFFC
At reset input
16
16
FFFB
FFFA
At completion of serial I/O1 data receive
16
16
FFF9
FFF8
At completion of serial I/O1 transmit shift
16
16
or when transmit buffer is empty
FFF7
FFF6
At completion of serial I/O2 data receive
16
16
FFF5
FFF4
At completion of serial I/O2 transmit shift
16
16
or when transmit buffer is empty
FFF3
FFF2
At detection of either rising or falling edge
16
16
of INT
FFF1
FFF0
At detection of either rising or falling edge
16
16
of INT
FFEF
FFEE
At falling of conjunction of input logical
16
16
level for port P0 (at input)
At detection of UART1 bus collision
detection
FFED
FFEC
At detection of either rising or falling edge
16
16
of CNTR
FFEB
FFEA
At detection of either rising or falling edge
16
16
of Capture 0 input
FFE9
FFE8
At detection of either rising or falling edge
16
16
of Capture 1 input
FFE7
FFE6
At compare matched
16
16
FFE5
FFE4
At timer X underflow
16
16
FFE3
FFE2
At timer A underflow
16
16
FFE1
FFE0
At timer B underflow
16
16
FFDF
FFDE
At completion of A/D conversion
16
16
At timer 1 underflow
FFDD
FFDC
At BRK instruction execution
16
16
Page 26 of 134
Interrupt request generating conditions
input
0
input
1
input
0
Remarks
Non-maskable
Valid only when serial I/O1 is selected
Valid only when serial I/O1 is selected
Valid only when serial I/O2 is selected
Valid only when serial I/O2 is selected
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
External interrupt (valid at falling, when
key-on wakeup interrupt is enabled)
When UART1 bus collision detection
interrupt is enabled.
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
Compare interrupt source is selected.
When A/D conversion interrupt is enabled.
STP release timer underflow
(When Timer 1 interrupt is enabled)
Non-maskable software interrupt
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