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7542 Group
(4) Pulse width measurement mode
In the pulse width measurement mode, the pulse width of the sig-
nal input to P1
/CNTR
pin is measured.
4
0
The operation of Timer X can be controlled by the level of the sig-
nal input from the CNTR
pin.
0
When the CNTR
active edge switch bit is "0", the signal selected
0
by the timer X count source selection bit is counted while the input
signal level of CNTR
pin is "H". The count is stopped while the
0
pin is "L". Also, when the CNTR
signal selected by the timer X count source selection bit is
counted while the input signal level of CNTR
is stopped while the pin is "H".
Timer X can stop counting by setting "1" to the timer X count stop
bit in any mode.
Also, when Timer X underflows, the timer X interrupt request bit is
set to "1".
Note on Timer X is described below;
Note on Timer X
(1) CNTR
interrupt active edge selection-1
0
CNTR
interrupt active edge depends on the CNTR
0
switch bit.
When this bit is "0", the CNTR
the falling edge of CNTR
pin input signal. When this bit is "1", the
0
CNTR
interrupt request bit is set to "1" at the rising edge of
0
CNTR
pin input signal.
0
(2) CNTR
interrupt active edge selection-2
0
According to the setting value of CNTR
the interrupt request bit may be set to "1".
When not requiring the interrupt occurrence synchronized with
these setting, take the following sequence.
Set the corresponding interrupt enable bit to "0" (disabled).
Set the active edge switch bit.
Set the corresponding interrupt request bit to "0" after 1 or more
instructions have been executed.
Set the corresponding interrupt enable bit to "1" (enabled).
Rev.3.02
Oct 31, 2006
REJ03B0006-0302
active edge switch bit is "1", the
0
pin is "L". The count
0
active edge
0
interrupt request bit is set to "1" at
0
active edge switch bit,
0
Page 31 of 134
b7
b0
T i m e r X m o d e r e g i s t e r
( T X M : a d d r e s s 0 0 2 B
T i m e r X o p e r a t i n g m o d e b i t s
b 1 b 0
0
0
1
1
C N T R
0 : I n t e r r u p t a t f a l l i n g e d g e
1 : I n t e r r u p t a t r i s i n g e d g e
T i m e r X c o u n t s t o p b i t
0 : C o u n t s t a r t
1 : C o u n t s t o p
P 0
3
0 : O u t p u t i n v a l i d ( I / O p o r t )
1 : O u t p u t v a l i d ( I n v e r t e d C N T R
N o t u s e d ( r e t u r n " 0 " w h e n r e a d )
Fig. 26 Structure of timer X mode register
b7
b0
Timer count source set register
(TCSS : address 002A
Timer X count source selection bits
b1 b0
0
0
1
1
Timer A count source selection bits
b4 b3 b2
0
0
0
0
1
1
1
1
Timer B count source selection bits
b7 b6 b5
0
0
0
0
1
1
1
1
Notes 1: f(X
) can be used as timer X count source when using
IN
a ceramic resonator or on-chip oscillator.
Do not use it at RC oscillation.
2: On-chip oscillator can be used when the on-chip oscillator
is enabled by bit 3 of CPUM.
Fig. 27 Timer count source set register
, i n i t i a l v a l u e : 0 0
1 6
0 : T i m e r m o d e
1 : P u l s e o u t p u t m o d e
0 : E v e n t c o u n t e r m o d e
1 : P u l s e w i d t h m e a s u r e m e n t m o d e
a c t i v e e d g e s w i t c h b i t
0
C o u n t a t r i s i n g e d g e
( i n e v e n t c o u n t e r m o d e )
C o u n t a t f a l l i n g e d g e
( i n e v e n t c o u n t e r m o d e )
/ T X
o u t p u t v a l i d b i t
O U T
0
, initial value: 00
16
0 : f(X
)/16
IN
1 : f(X
)/2
IN
0 : f(X
) (Note 1)
IN
1 : Not available
0
0 : f(X
)/16
IN
0
1 : f(X
)/2
IN
1
0 : f(X
)/32
IN
1
1 : f(X
)/64
IN
0
0 : f(X
)/128
IN
0
1 : f(X
)/256
IN
1
0 : On-chip oscillator output (Note 2)
1
1 : Not available
0
0 : f(X
)/16
IN
0
1 : f(X
)/2
IN
1
0 : f(X
)/32
IN
1
1 : f(X
)/64
IN
0
0 : f(X
)/128
IN
0
1 : f(X
)/256
IN
1
0 : Timer A underflow
1
1 : Not available
)
1 6
o u t p u t )
)
16
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