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7542 Group
(1) Port P0
0
Direction
register
Port latch
Data bus
Capture 0 input
Capture 0 input control
To key input interrupt
generating circuit
(3) Port P0
3
P0
/TX
output valid
3
OUT
Direction
register
Data bus
Port latch
Timer output
To key input interrupt
generating circuit
(5) Port P0
5
Serial I/O2 enable bit
Transmit enable bit
Direction
register
Data bus
Port latch
Serial I/O2 output
To key input interrupt
generating circuit
(7) Port P0
7
Serial I/O2 mode selection bit
Serial I/O2 enable bit
S
output enable bit
RDY2
Direction
register
Data bus
Port latch
Serial I/O2 ready output
To key input interrupt
generating circuit
Fig. 20 Block diagram of ports (1)
Rev.3.02
Oct 31, 2006
REJ03B0006-0302
Pull-up control
Drive capacity
control
P0
key-on wakeup
0
selection bit
Pull-up control
Drive capacity
control
Pull-up control
Drive capacity
control
Pull-up control
Drive capacity
control
Page 21 of 134
(2) Ports P0
P0
1,
2
Compare output control
Direction
register
Data bus
Port latch
Compare output
To key input interrupt
generating circuit
(4) Port P0
4
Serial I/O2 enable bit
Receive enable bit
Direction
register
Data bus
Port latch
Serial I/O2 input
To key input interrupt
generating circuit
(6) Port P0
6
Serial I/O2 synchronous
clock selection bit
Serial I/O2 enable bit
Serial I/O2 mode selection bit
Serial I/O2 enable bit
Direction
register
Data bus
Port latch
Serial I/O2 clock output
Serial I/O2 clock input
To key input interrupt
generating circuit
Pull-up control
Drive capacity
control
Pull-up control
Drive capacity
control
P0
key-on wakeup
4
selection bit
Pull-up control
Drive capacity
control
P0
key-on wakeup
6
selection bit
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