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7542 Group
Interrupts
Interrupts occur by 18 different sources : 6 external sources, 11 in-
ternal sources and 1 software source.
Interrupt control
All interrupts except the BRK instruction interrupt have an interrupt
request bit and an interrupt enable bit, and they are controlled by
the interrupt disable flag. When the interrupt enable bit and the in-
terrupt request bit are set to "1" and the interrupt disable flag is set
to "0", an interrupt is accepted.
The interrupt request bit can be cleared by program but not be set.
The interrupt enable bit can be set and cleared by program.
The reset and BRK instruction interrupt can never be disabled with
any flag or bit. All interrupts except these are disabled when the
interrupt disable flag is set.
When several interrupts occur at the same time, the interrupts are
received according to priority.
Interrupt operation
Upon acceptance of an interrupt the following operations are auto-
matically performed:
1. The processing being executed is stopped.
2. The contents of the program counter and processor status reg-
ister are automatically pushed onto the stack.
3. The interrupt disable flag is set and the corresponding interrupt
request bit is cleared.
4. Concurrently with the push operation, the interrupt destination
address is read from the vector table into the program counter.
[Interrupt source set register] INTSET
When two interrupt sources are assigned to the same interrupt
vector, the valid/invalid of each interrupt is set by this register.
When both two interrupt sources are set to be valid, which inter-
rupt request occurs is confirmed by the next interrupt source
discrimination register.
[Interrupt source discrimination register] INTDIS
When two interrupt sources are assigned to the same interrupt
vector, which interrupt source occurs is confirmed by this register.
If an interrupt request of a key-on wakeup, UART1 bus collision
detection, A/D conversion or timer 1 occurs, an interrupt discrimi-
nation bit is set to "1" regardless of valid/invalid state by the
interrupt source set register.
However, when the interrupt valid bit of an interrupt source set
register is "0" (invalid), the interrupt request bit of an interrupt con-
trol register is not set to "1."
Moreover, since an interrupt discrimination bit is not automatically
cleared to "0" by interrupt, please clear it by program.
An interrupt discrimination bit can be cleared to "0" by program but
not be set to "1."
Rev.3.02
Oct 31, 2006
REJ03B0006-0302
Page 25 of 134
[Interrupt edge selection register] INTEDGE
The valid edge of external interrupt INT
by the interrupt edge selection bit, respectively.
For the external interrupt INT
P3
/INT
can be selected by the INT
6
1
However, since there is no P3
PWQN0036KA-A package, select P3
wakeup selection bit, enable/disable of a key-on wakeup of P0
P0
, and P0
pins can be selected, respectively.
4
6
Notes on use
(1) When setting the followings, the interrupt request bit may be
set to "1".
•When switching external interrupt active edge
Related register:
Interrupt edge selection register (address 003A
Timer X mode register (address 002B
Capture mode register (address 0020
When not requiring the interrupt occurrence synchronized with
these setting, take the following sequence.
Set the corresponding interrupt enable bit to "0" (disabled).
Set the interrupt edge select bit (active edge switch bit, trigger
mode bit).
Set the corresponding interrupt request bit to "0" after 1 or more
instructions have been executed.
Set the corresponding interrupt enable bit to "1" (enabled).
(2) Use a LDM instruction to clear an interrupt discrimination bit.
LDM #$0n, $0Bn
Set the following values to "n"
"0": an interrupt discrimination bit to clear
"1": other interrupt discrimination bits
Ex.) When a key-on wakeup interrupt discrimination bit is
cleared;
LDM #00001110B and $0B.
and INT
can be selected
0
1
, the external input pin P3
1
3
input port selection bit.
1
/INT
pin in the 32-pin version
6
1
/INT
pin. By the key-on
3
1
)
16
)
16
)
16
/INT
or
1
,
0
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