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Renesas 7542 Manual

Renesas 7542 Manual

Single-chip 8-bit cmos microcomputer
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7542 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
DESCRIPTION
The 7542 Group is the 8-bit microcomputer based on the 740 fam-
ily core technology.
The 7542 Group has serial I/Os, 8-bit timers, 16-bit timers, and an
A/D converter, and is useful for control of home electric appliances
and office automation equipment.
FEATURES
Basic machine-language instructions ...................................... 71
•
The minimum instruction execution time ............................. 0.25 µs
•
(at 8 MHz oscillation frequency, double-speed mode for the
shortest instruction)
Memory size
•
Flash memory version: ROM ..................... 16 to 32K + 4K bytes
RAM ..................................... 1024 bytes
Mask ROM version:
ROM ............................. 8K to 16K bytes
RAM ............................ 384 to 512 bytes
RSS version
RAM ..................................... 1024 bytes
Programmable I/O ports
•
29 (25 in 32-pin version and PWQN0036KA-A package version)
Interrupts ................................................. 18 sources, 16 vectors
•
Timers ............................................................................. 8-bit
•
...................................................................................... 16-bit
• Output compare ............................................................ 4-channel
• Input capture ................................................................ 2-channel
Serial I/O ...................... 8-bit
•
A/D converter ............................................... 10-bit
•
..... (6 channels in 32-pin version and PWQN0036KA-A package
version)
Clock generating circuit ............................................. Built-in type
•
(low-power dissipation by an on-chip oscillator)
(connected to external ceramic resonator or quartz-crystal
Rev.3.02
Oct 31, 2006
REJ03B0006-0302
2 (UART or Clock-synchronized)
8 channels
oscillator permitting RC oscillation)
Page 1 of 134
Watchdog timer ............................................................ 16-bit
•
Power source voltage
•
X
oscillation frequency at ceramic oscillation, in double-speed mode
IN
At 8 MHz .................................................................... 4.5 to 5.5 V
X
oscillation frequency at ceramic oscillation, in high-speed mode
IN
At 8 MHz .................................................................... 4.0 to 5.5 V
At 4 MHz .................................................................... 2.4 to 5.5 V
At 2 MHz .................................................................... 2.2 to 5.5 V
X
oscillation frequency at RC oscillation in high-speed mode or
IN
middle-speed mode
At 4 MHz .................................................................... 4.0 to 5.5 V
At 2 MHz .................................................................... 2.4 to 5.5 V
At 1 MHz .................................................................... 2.2 to 5.5 V
Power dissipation ................................................ 27.5 mW (Typ.)
•
Operating temperature range ................................... –20 to 85 °C
•
(–40 to 85 °C for extended operating temperature version)
(–40 to 125 °C for extended operating temperature 125 °C ver-
sion (Note))
Note: In this version, the operating temperature range and total time are
limited as follows;
55 °C to 85 °C: within total 6000 hours,
2
85 °C to 125 °C: within total 1000 hours.
2
APPLICATION
Office automation equipment, factory automation equipment, home
electric appliances, consumer electronics, car, etc.
REJ03B0006-0302
Rev.3.02
Oct 31, 2006
1

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Summary of Contents for Renesas 7542

  • Page 1 Rev.3.02 Oct 31, 2006 DESCRIPTION Watchdog timer ............16-bit • The 7542 Group is the 8-bit microcomputer based on the 740 fam- Power source voltage • ily core technology. oscillation frequency at ceramic oscillation, in double-speed mode The 7542 Group has serial I/Os, 8-bit timers, 16-bit timers, and an At 8 MHz ..............
  • Page 2 7542 Group PIN CONFIGURATION (TOP VIEW) 24 23 22 (LED (LED RDY2 M37542Mx-XXXGP /CAP (LED )/INT M37542MxT-XXXGP (LED )/CMP M37542MxV-XXXGP (LED )/CMP CLK1 M37542FxGP (LED )/CAP RDY1 M37542F8TGP /CNTR M37542F8VGP Outline PLQP0032GB-A (32P6U-A) Fig. 1 Pin configuration (Package type: PLQP0032GB-A)
  • Page 3 7542 Group CLK1 RDY1 /CAP /CNTR (LED RDY2 (LED CLK2 (LED )/TxD (LED )/RxD (LED )/TX (LED )/CMP (LED )/CMP (LED )/CAP (LED )/INT RESET (LED (LED )/INT (LED )/CMP (LED )/CMP (LED )/CAP Package type: PRDP0032BA-A (32P4B) Fig. 3 Pin configuration (Package type: PRDP0032BA-A)
  • Page 4 7542 Group /CNTR RDY1 CLK1 /CAP (LED RDY2 (LED CLK2 (LED )/TxD (LED )/RxD (LED )/TX (LED )/CMP (LED )/CMP (LED )/CAP (LED )/INT (LED )/INT RESET (LED (LED (LED )/INT (LED )/CMP (LED )/CMP (LED )/CAP Package type 42S1M Fig.
  • Page 5 7542 Group Table 1 Performance overview Parameter Function Number of basic instructions Instruction execution time 0.25 µs (Minimum instruction, oscillation frequency 8 MHz: double-speed mode) Oscillation frequency 8 MHz (max.) Memory sizes Mask ROM 8 K to 16 K bytes...
  • Page 6 7542 Group FUNCTIONAL BLOCK Fig. 6 Functional block diagram (Package type: PLQP0032GB-A) Rev.3.02 Oct 31, 2006 Page 6 of 134 REJ03B0006-0302...
  • Page 7 7542 Group Fig. 7 Functional block diagram (Package type: PRSP0036GA-A) Rev.3.02 Oct 31, 2006 Page 7 of 134 REJ03B0006-0302...
  • Page 8 7542 Group Fig. 8 Functional block diagram (Package type: PRDP0032BA-A) Rev.3.02 Oct 31, 2006 Page 8 of 134 REJ03B0006-0302...
  • Page 9 7542 Group Fig. 9 Functional block diagram (Package type: PWQN0036KA-A) Rev.3.02 Oct 31, 2006 Page 9 of 134 REJ03B0006-0302...
  • Page 10 7542 Group PIN DESCRIPTION Table 2 Pin description Name Function Function expect a port function Vcc, Vss Power source Mask ROM version (Note 1) Apply voltage of 2.2 to 5.5 V to Vcc, and 0 V to Vss. FLASH ROM version Apply voltage of 2.7 to 5.5 V to Vcc, and 0 V to Vss.
  • Page 11 7542 Group GROUP EXPANSION Memory size Renesas plans to expand the 7542 group as follow: Flash memory size ........16 to 32 K + 4 K bytes Mask ROM size ........... 8 K to 16 K bytes Memory type RAM size ............384 to 1024 bytes Support for Mask ROM version, Flash memory version, and Emu- lator MCU .
  • Page 12 7542 Group Currently supported products are listed below. Table 3 List of supported products ROM size (bytes) RAM size Product Package Remarks ROM size for User ( ) (bytes) PRDP0032BA-A Mask ROM version M37542M2-XXXSP 8192 PWQN0036KA-A Mask ROM version M37542M2-XXXHP...
  • Page 13 7542 Group FUNCTIONAL DESCRIPTION Stack pointer (S) The stack pointer is an 8-bit register used during subroutine calls Central Processing Unit (CPU) and interrupts. The stack is used to store the current address data The MCU uses the standard 740 family instruction set. Refer to...
  • Page 14 7542 Group On-going Routine Interrupt request (Note) M (S) Execute JSR (S – 1) Store Return Address on Stack M (S) M (S) (S – 1) Store Return Address (S – 1) on Stack Store Contents of Processor M (S)
  • Page 15 7542 Group Processor status register (PS) (5) Break flag (B) The processor status register is an 8-bit register consisting of The B flag is used to indicate that the current interrupt was gener- flags which indicate the status of the processor after an arithmetic ated by the BRK instruction.
  • Page 16 7542 Group [CPU mode register] CPUM The CPU mode register contains the stack page selection bit, etc.. CPU mode register This register is allocated at address 003B (CPUM: address 003B , initial value: 80 Processor mode bits (Note 1) b1 b0...
  • Page 17 7542 Group Memory Special function register (SFR) area Zero page The SFR area in the zero page contains control registers such as The 256 bytes from addresses 0000 to 00FF are called the I/O ports and timers. zero page area. The internal RAM and the special function regis- ters (SFR) are allocated to this area.
  • Page 18 7542 Group Port P0 (P0) Capture mode register (CAPM) 0000 0020 0001 Port P0 direction register (P0D) 0021 Compare output mode register (CMOM) Port P1 (P1) 0002 0022 Capture/compare status register (CCSR) Port P1 direction register (P1D) Compare interrupt source set register (CISR)
  • Page 19 7542 Group I/O Ports [Direction registers] PiD P o r t P 0 P 3 d r i v e c a p a c i t y c o n t r o l r e g i s t e r...
  • Page 20 7542 Group Table 6 I/O port function table Name I/O format Non-port function SFRs related each pin Diagram (LED )/CAP I/O port P0 •CMOS compatible • Capture function input Capture/Compare port register input level (Note 1) • Key input interrupt Interrupt edge selection register •CMOS 3-state output...
  • Page 21 7542 Group (1) Port P0 (2) Ports P0 Pull-up control Pull-up control Compare output control Direction Direction register register Port latch Data bus Port latch Data bus Drive capacity Drive capacity control control Capture 0 input Capture 0 input control...
  • Page 22 7542 Group (8) Port P1 (9) Port P1 Serial I/O1 enable bit P-channel output disable bit Receive enable bit Serial I/O1 enable bit Direction Transmit enable bit register Direction Data bus Port latch register , P1 , P1 input level...
  • Page 23 7542 Group (15) Ports P3 (14) Port P3 Pull-up control Pull-up control Compare output control Direction Direction register register Data bus Port latch Data bus Port latch Drive capacity Drive capacity control control Capture 1 input Compare output Capture 1 input control...
  • Page 24 7542 Group Termination of unused pins Especially, when expecting low consumption current (at STP or WIT instruction execution etc.), pull-up or • Termination of common pins pull-down input ports to prevent through current I/O ports: Select an input port or an output port and follow (built-in resistor can be used).
  • Page 25 7542 Group Interrupts [Interrupt edge selection register] INTEDGE Interrupts occur by 18 different sources : 6 external sources, 11 in- The valid edge of external interrupt INT and INT can be selected ternal sources and 1 software source. by the interrupt edge selection bit, respectively.
  • Page 26 7542 Group Table 8 Interrupt vector address and priority Vector addresses (Note 1) Interrupt source Priority Interrupt request generating conditions Remarks High-order Low-order Reset (Note 2) FFFD FFFC At reset input Non-maskable Serial I/O1 receive FFFB FFFA At completion of serial I/O1 data receive...
  • Page 27 7542 Group Key-on wakeup interrupt discrimination bit Key-on wakeup interrupt request Key-on wakeup interrupt valid bit Key-on wakeup/ UART1 bus UART1 bus collision collision detection detection interrupt UART1 bus collision detection interrupt request bit interrupt request discrimination bit UART1 bus collision detection...
  • Page 28 7542 Group Interrupt request register 1 Interrupt source set register (IREQ1 : address 003C , initial value : 00 (INTSET: address 000A , initial value: 00 Key-on wakeup interrupt valid bit Serial I/O1 receive interrupt request bit UART1 bus collision detection interrupt valid bit...
  • Page 29 7542 Group Key Input Interrupt (Key-On Wake-Up) A key-on wake-up interrupt request is generated by applying “L” level to any pin of port P0 that has been set to input mode. In other words, it is generated when the AND of input level goes from “1”...
  • Page 30 Timers Timer X is an 8-bit timer and counts the prescaler X output. The 7542 Group has 4 timers: timer 1, timer X, timer A and timer When Timer X underflows, the timer X interrupt request bit is set to “1”.
  • Page 31 7542 Group (4) Pulse width measurement mode T i m e r X m o d e r e g i s t e r In the pulse width measurement mode, the pulse width of the sig- ( T X M : a d d r e s s 0 0 2 B...
  • Page 32 7542 Group Data bus Prescaler 1 latch (8) Timer 1 latch (8) Timer 1 interrupt Prescaler 1 (8) Timer 1 (8) 1/16 request “00” Data bus “01” “11” Clock Frequency Timer X count division ratio divider source selection bits selection bits...
  • Page 33 7542 Group Timer A,B Notes on Timer A, B Timer A and Timer B are 16-bit timers and counts the signal which (1) Setting of timer value is the oscillation frequency selected by setting of the timer count When “1: Write to only latch” is set to the timer A (B) write control source set register (TCSS).
  • Page 34 7542 Group T i m e r A , B m o d e r e g i s t e r Timer count source set register ( T A B M : a d d r e s s 0 0 1 D...
  • Page 35 Output compare Notes on Output Compare 7542 group has 4-output compare channels. Each channel (0 to 3) • When the selected source timer of each compare channel is has the same function and can be used to output waveform by us- stopped, written data to compare register is loaded to the com- ing count value of either Timer A or Timer B.
  • Page 36 7542 Group C a p t u r e / C o m p a r e p o r t r e g i s t e r C a p t u r e / C o m p a r e s t a t u s r e g i s t e r...
  • Page 37 7542 Group Compare latch 00 Compare latch 01 /CMP Timer A latch Wave latch channel 0 Timer A counter Compare 0 timer source bit Timer B counter Compare channel 0 Timer B latch Compare channel 1 /CMP Compare channel 2...
  • Page 38 7542 Group Data bus Compare register write pointer (0012 , bits 0 to 2) /CMP port Compare buffer 01 (16) Compare buffer 00 (16) Compare latch 00, 01 Compare 0 output re-load bit port bit (0014 , bit 0) (001E...
  • Page 39 7542 Group Timer count clock Re-load the count value Timer underflow Timer count value 000C 000B 000A 0009 0008 0007 0006 0005 0004 0003 0002 0001 0000 000F 000E 000D 000C 000B Compare latch 00 000B Compare latch 01 0005...
  • Page 40 7542 Group Carrier wave generated by Compare 0 Timer A count clock Timer A underflow Timer A count value 0004 0003 0002 0001 0000 0007 0006 0005 0004 0003 0002 0001 0000 0007 0006 0005 0004 0003 Compare latch 00...
  • Page 41 7542 Group 1. When Compare 0 output level latch is “Positive”, Compare 1 output level latch is “Positive”. Compare 0 output Compare 1 output Modulation output 2. When Compare 0 output level latch is “Negative”, Compare 1 output level latch is “Positive”.
  • Page 42 Input capture Notes on Input Capture 7542 group has 2-input capture channels. Each channel (0 and 1) • If the capture trigger is input while the capture register (low-order has the same function and can be used to capture count value of and high-order) is in read, captured value is changed between either Timer A or Timer B.
  • Page 43 7542 Group Capture software trigger register C a p t u r e r e g i s t e r 0 ( L o w - o r d e r ) (CSTR : address 0013 , initial value: 00...
  • Page 44 7542 Group /CAP Trigger input channel 0 Capture latch 00 /CAP Timer A latch Capture latch 01 Ring /512 Timer A counter Capture 0 timer source bit Timer B counter /CAP Capture channel 0 Ring Timer B latch Capture channel 1 /512 Fig.
  • Page 45 7542 Group Re-load the timer count value Timer underflow Capture input wave Timer count value 000C 000B 000A 0009 0008 0007 0006 0005 0004 0003 0002 0001 0000 000F 000E 000D 000C 000B Overwrite Capture latch 00 XXXX 000A 0001...
  • Page 46 Serial I/O (1) Clock Synchronous Serial I/O1 Mode The 7542 Group has Serial I/O1 and Serial I/O2. Except that Serial Clock synchronous serial I/O1 mode can be selected by setting I/O1 has the bus collision detection function and the T...
  • Page 47 7542 Group The transmit and receive shift registers each have a buffer, but the (2) Asynchronous Serial I/O1 (UART) Mode two buffers have the same address in memory. Since the shift reg- Clock asynchronous serial I/O mode (UART) can be selected by...
  • Page 48 7542 Group [Transmit buffer register 1/receive buffer register 1 (TB1/ Notes on Serial I/O1 RB1)] 0018 • Serial I/O interrupt The transmit buffer register and the receive buffer register are lo- When setting the transmit enable bit to “1”, the serial I/O transmit cated at the same address.
  • Page 49 7542 Group S e r i a l I / O 1 s t a t u s r e g i s t e r S e r i a l I / O 1 c o n t r o l r e g i s t e r...
  • Page 50 7542 Group Bus collision detection (SIO1) Interrupt source set register SIO1 can detect a bus collision by setting UART1 bus collision de- (INTSET: address 000A , initial value: 00 tection interrupt enable bit. Key-on wakeup interrupt valid bit When transmission is started in the clock synchronous or asyn-...
  • Page 51 7542 Group Serial I/O2 (1) Clock Synchronous Serial I/O2 Mode Serial I/O2 can be used as either clock synchronous or asynchro- Clock synchronous serial I/O2 mode can be selected by setting nous (UART) serial I/O. A dedicated timer is also provided for the serial I/O2 mode selection bit of the serial I/O2 control register baud rate generation.
  • Page 52 7542 Group The transmit and receive shift registers each have a buffer, but the (2) Asynchronous Serial I/O2 (UART) Mode two buffers have the same address in memory. Since the shift reg- Clock asynchronous serial I/O mode (UART) can be selected by...
  • Page 53 7542 Group [Transmit buffer register 2/receive buffer register 2 (TB2/ Notes on Serial I/O2 RB2)] 002E • Serial I/O interrupt The transmit buffer register and the receive buffer register are lo- When setting the transmit enable bit to “1”, the serial I/O transmit cated at the same address.
  • Page 54 7542 Group S e r i a l I / O 2 s t a t u s r e g i s t e r S e r i a l I / O 2 c o n t r o l r e g i s t e r...
  • Page 55 7542 Group A/D Converter The functional blocks of the A/D converter are described below. A/D control register (ADCON : address 0034 , initial value: 10 Analog input pin selection bits [A/D conversion register] AD 000 : P2 The A/D conversion register is a read-only register that stores the 001 : P2 result of A/D conversion.
  • Page 56 7542 Group Data bus A/D control register (Address 0034 A/D interrupt request A/D control circuit A/D conversion register (high-order) (Address 0036 Comparator A/D conversion register (low-order) (Address 0035 Resistor ladder Fig. 67 Block diagram of A/D converter Rev.3.02 Oct 31, 2006...
  • Page 57 7542 Group Watchdog Timer Operation of STP instruction function selection bit The watchdog timer gives a means for returning to a reset status When “0” is set to STP instruction function selection bit, system when the program fails to run on its normal loop due to a runaway.
  • Page 58 7542 Group Reset Circuit Poweron The 7542 group starts operation by the on-chip oscillator after sys- (Note) tem is released from reset. Power source voltage RESET Accordingly, when the rising of power supply voltage passes 2.2V, set the reset input voltage to become below 0.2Vcc (0.44V).
  • Page 59 7542 Group Address Register contents 0001 Port P0 direction register (P0D) 0003 Port P1 direction register (P1D) 0005 Port P2 direction register (P2D) 0007 Port P3 direction register (P3D) 000A Interrupt source set register (INTSET) Interrupt source discrimination register (INTDIS)
  • Page 60 7542 Group Clock Generating Circuit Note: The clock frequency of the An oscillation circuit can be formed by connecting a resonator be- on-chip oscillator depends tween X and X , and an RC oscillation circuit can be formed M37542 on the supply voltage and by connecting a resistor and a capacitor.
  • Page 61 7542 Group (1) Oscillation control • CPU mode register • Stop mode Bits 5, 1 and 0 of CPU mode register are used to select oscillation When the STP instruction is executed, the internal clock φ stops at mode and to control operation modes of the microcomputer. In or- an “H”...
  • Page 62 7542 Group On-chip oscillation division ratio At on-chip oscillator mode, division ratio of on-chip oscillator for CPU clock is selected by setting value of on-chip oscillation divi- sion ratio selection register. The division ratio of on-chip oscillation for CPU clock is selected from among 1/1, 1/2, 1/8, 1/128. The op- eration clock for the peripheral function block is not changed by setting value of this register.
  • Page 63 7542 Group (Note) Clock division ratio selection bits Middle-, high-, double-speed mode Timer 1 Prescaler 1 On-chip oscillator mode Clock division ratio selection bits Middle-speed mode Timing φ High-speed mode (Internal Double-speed mode clock) On-chip oscillator division /128 1/16 On-chip oscillator...
  • Page 64 7542 Group STP mode ) oscillation: stop On-chip oscillator: stop Interrupt Interrupt Interrupt instruction instruction instruction ) oscillation: enabled ) oscillation: enabled Interrupt ) oscillation: enabled ) oscillation: stop On-chip oscillator: stop On-chip oscillator: enabled On-chip oscillator: enabled On-chip oscillator: enabled...
  • Page 65 7542 Group Oscillation stop detection circuit The oscillation stop detection circuit is used for reset occurrence MISRG(address 0038 , initial value: 00 when a ceramic resonator or RC oscillation circuit stops by dis- Oscillation stabilization time set bit after connection. To use this circuit, set an on-chip oscillator to be in release of the STP instruction active.
  • Page 66 7542 Group CPUM Reset (Note 4) released ) oscillation: enabled ) oscillation: enabled RESET state 1 State 3 State 2 On-chip oscillator: enabled On-chip oscillator: enabled (Note 4) ) oscillation: enabled CPUM On-chip oscillator: enabled MISRG MISRG MISRG MISRG Applied “L” to RESET pin...
  • Page 67 D to “1”, then execute the ADC instruction or SBC instruction. In For the mask ROM confirmation and the mark specifications, this case, execute SEC instruction, CLC instruction or CLD in- refer to the "Renesas Technology Corp." Homepage struction after executing one instruction before the ADC instruction (http://www.renesas.com/en/rom).
  • Page 68 7542 Group NOTES ON USE (3) Wiring for clock input/output pins • Make the length of wiring which is connected to clock I/O pins as Countermeasures against noise short as possible. • Make the length of wiring (within 20 mm) across the grounding lead of a capacitor which is connected to an oscillator and the 1.
  • Page 69 7542 Group 2. Connection of bypass capacitor across V line and V line 3. Wiring to analog input pins Connect an approximately 0.1 µ F bypass capacitor across the V • Connect an approximately 100 Ω to 1 kΩ resistor to an analog...
  • Page 70 7542 Group (3) Oscillator protection using Vss pattern 4. Oscillator concerns As for a two-sided printed circuit board, print a Vss pattern on the Take care to prevent an oscillator that generates clocks for a mi- underside (soldering side) of the position (on the component side) crocomputer operation from being affected by other signals.
  • Page 71 7542 Group 5. Setup for I/O ports <The main routine> Setup I/O ports using hardware and software as follows: • Assigns a single byte of RAM to a software watchdog timer (SWDT) and writes the initial value N in the SWDT once at each <Hardware>...
  • Page 72 This Boot ROM area can be rewritten in only parallel I/O Summary mode. Table 9 lists the summary of the 7542 Group (flash memory ver- sion). Table 9 Summary of 7542 group’s flash memory version Item...
  • Page 73 7542 Group 32K bytes ROM Product 16K bytes ROM Product 0000 0000 User ROM area SFR area SFR area SFR area 7000 7000 0040 0040 Data block B : Data block B : 2K bytes 2K bytes Internal RAM area...
  • Page 74 7542 Group [Flash memory control registers (FMCR0 to FMCR2)] Bit 3 of the flash memory control register 0 is the flash memory re- 0FE0 to 0FE2 set bit used to reset the control circuit of internal flash memory. Figure 95 shows the flash memory control register 0.
  • Page 75 7542 Group Figure 96 shows the flash memory control register 1. Bit 0 of the flash memory control register 1 is the Erase suspend Flash memory control register 1 (FMCR1: address : 0FE1 : initial value: 40 enable bit. By setting this bit to “1”, the erase suspend mode to...
  • Page 76 7542 Group Figure 98 shows a flowchart for setting/releasing CPU rewrite mode. Start Single-chip mode or Boot mode Set CPU mode register (Note 1) Transfer CPU rewrite mode control program to internal RAM Jump to control program transferred to internal RAM...
  • Page 77 7542 Group Software Commands The RY/BY status flag of the flash memory control register is “0” Table 11 lists the software commands. during write operation and “1” when the write operation is com- After setting the CPU rewrite mode select bit to “1”, execute a soft- pleted as is the status register bit 7.
  • Page 78 7542 Group • Block Erase Command (20 By writing the command code “20 ” in the first bus cycle and the Start confirmation command code “D0 ” and the block address in the second bus cycle that follows, the block erase (erase and erase verify) operation starts for the block address of the flash memory Write “20...
  • Page 79 7542 Group Status Register •Erase status (SR5) The status register shows the operating status of the flash The erase status indicates the operating status of erase operation. memory and whether erase operations and programs ended suc- If an erase error occurs, it is set to “1”. When the erase status is cessfully or in error.
  • Page 80 7542 Group Full Status Check By performing full status check, it is possible to know the execu- tion results of erase and program operations. Figure 101 shows a full status check flowchart and the action to be taken when each error occurs.
  • Page 81 7542 Group Functions To Inhibit Rewriting Flash If one or both of the pair of ROM code protect bits is set to “0”, the Memory Version ROM code protect is turned on, so that the contents of internal To prevent the contents of internal flash memory from being read flash memory are protected against readout and modification.
  • Page 82 7542 Group (2) ID Code Check Function Use this function in standard serial I/O mode. When the contents of the flash memory are not blank, the ID code sent from the pro- grammer is compared with the ID code written in the flash memory to see if they match.
  • Page 83 The parallel I/O mode is used to input/output software commands, address and data in parallel for operation (read, program and erase) to internal flash memory. Use the external device (writer) only for 7542 Group (flash memory version). For details, refer to the user’s manual of each writer manufacturer.
  • Page 84 CNVss pin to “L” level.) This control program is written in the Boot ROM area when the product is shipped from Renesas. Accordingly, make note of the fact that the standard serial I/O mode cannot be used if the Boot ROM area is rewritten in parallel I/O mode.
  • Page 85 7542 Group (1) Standard serial I/O mode 1 Table 13 Description of pin function (standard serial I/O mode 1) Pin name Signal name Function Power supply Apply 2.7 to 5.5 V to the Vcc pin and 0 V to the Vss pin.
  • Page 86 7542 Group "L" input 24 23 22 BUSY (LED (LED RDY2 /CAP (LED )/INT M37542FxGP (LED )/CMP "H" input M37542F8TGP (LED )/CMP CLK1 (LED )/CAP RDY1 M37542F8VGP /CNTR Note RESET Note. Connect the oscillation circuit to X and X (Package type: PLQP0032GB-A) Fig.
  • Page 87 7542 Group CLK1 RDY1 /CAP /CNTR BUSY (LED RDY2 (LED CLK2 (LED )/TxD (LED )/RxD (LED )/TX (LED )/CMP (LED )/CMP (LED )/CAP (LED )/INT RESET "L" input RESET (LED (LED )/INT (LED )/CMP "H" input Note (LED )/CMP (LED )/CAP Note.
  • Page 88 7542 Group • Standard serial I/O mode 1 Figure 107 shows the handling example of control pins on the user system board when the standard serial I/O mode 1 is used. Refer to the serial programmer manual of your programmer to handle pins controlled by the programmer.
  • Page 89 7542 Group Power source RESET (RP) (CEB) (BUSY) (Note) CLK2 (TxD (RxD td(port-CNV td(CNV -RESET) td(RESET-SCLK) th(CNV -RESET) th(CNV -port) Note: Keep input of P0 “H” until P0 turns “L”. Symbol Ratings Unit Min. Typ. Max. td(port-CNVss) td(CNVss-RESET) td(RESET-SCLK) 0.05...
  • Page 90 7542 Group (2) Standard serial I/O mode 2 Table 14 Description of pin function (standard serial I/O mode 2) Pin name Signal name Function Power supply Apply 2.7 to 5.5 V to the Vcc pin and 0 V to the Vss pin.
  • Page 91 7542 Group input “L” input "L" 24 23 22 BUSY (LED (LED RDY2 /CAP (LED )/INT M37542FxGP (LED )/CMP “H” input M37542F8TGP (LED )/CMP CLK1 (LED )/CAP RDY1 M37542F8VGP /CNTR Note RESET Note. Connect the oscillation circuit to X and X (Package type: PLQP0032GB-A) Fig.
  • Page 92 7542 Group CLK1 RDY1 /CAP /CNTR BUSY (LED RDY2 (LED "L" input CLK2 (LED )/TxD (LED )/RxD (LED )/TX (LED )/CMP (LED )/CMP (LED )/CAP (LED )/INT "L" input (LED )/INT RESET RESET (LED (LED (LED )/INT (LED )/CMP "H" input...
  • Page 93 7542 Group • Standard serial I/O mode 2 Figure 112 shows the handling example of control pins on the user system board when the standard serial I/O mode 2 is used. Refer to the serial programmer manual of your programmer to handle pins controlled by the programmer.
  • Page 94 7542 Group Power source RESET (RP) (CEB) CLK2 (TxD (RxD td(port-CNV td(CNV -RESET) th(CNV -RESET) th(CNV -port) Symbol Ratings Unit Note: In the standard serial I/O2, set P0 and P0 as follows; Min. Typ. Max. : input “L” level. td(port-CNVss) : BUSY signal output pin.
  • Page 95 7542 Group ELECTRICAL CHARACTERISTICS 1.7542Group (General purpose) Applied to: M37542M4/M2-XXXFP/SP/GP/HP, M37542F8FP/SP/GP/HP(Note), M37542F4FP/SP/GP Note: M37542F8HP: Only ES version (MP: no plan) Absolute Maximum Ratings (General purpose) Table 15 Absolute maximum ratings (General purpose) Symbol Parameter Conditions Ratings Unit Power source voltage –0.3 to 6.5...
  • Page 96 7542 Group Recommended Operating Conditions (General purpose) Table 16 Recommended operating conditions (1) (General purpose) (FLASH ROM version: V = 2.7 to 5.5V, Mask ROM version: V = 2.2 to 5.5 V, V = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
  • Page 97 7542 Group Recommended Operating Conditions (General purpose) (continued) Table 17 Recommended operating conditions (2) (General purpose) (FLASH ROM version: V = 2.7 to 5.5V, Mask ROM version: V = 2.2 to 5.5 V, V = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
  • Page 98 7542 Group Electrical Characteristics (General purpose) Table 18 Electrical characteristics (1) (General purpose) (FLASH ROM version: V = 2.7 to 5.5V, Mask ROM version: V = 2.2 to 5.5 V, V = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
  • Page 99 7542 Group Electrical Characteristics (General purpose)(continued) Table 19 Electrical characteristics (2) (General purpose) (FLASH ROM version: V = 2.7 to 5.5V, Mask ROM version: V = 2.2 to 5.5 V, V = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
  • Page 100 3.0 V or less at the low temperature, the AD conversion accuracy may be very lower than at room temperature. When system is used at low temperature, that V is 3.0 V or more is recommended. Electrical Characteristics of 7542 Group Flash Memory (General purpose) Table 21 Electrical Characteristics of 7542 Group Flash Memory (General purpose) Limits Test Symbol...
  • Page 101 7542 Group Timing Requirements (General purpose) Table 22 Timing requirements (1) (General purpose) (FLASH ROM version: V = 4.0 to 5.5V, Mask ROM version: V = 4.0 to 5.5 V, V = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
  • Page 102 7542 Group Table 24 Timing requirements (3) (General purpose) (Mask ROM version: V = 2.2 to 5.5 V, V = 0 V, Ta = –20 to 85 °C, unless otherwise noted) (This is only for the mask ROM version.) Limits...
  • Page 103 7542 Group Switching Characteristics (General purpose) Table 25 Switching characteristics (1) (General purpose) (FLASH ROM version: V = 4.0 to 5.5V, Mask ROM version: V = 4.0 to 5.5 V, V = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
  • Page 104 7542 Group (CNTR (CNTR (CNTR CNTR 0.8V 0.2V (CNTR (CNTR , INT 0.8V 0.2V , CAP (RESET) RESET 0.2V 0.8V 0.2V CLK1 CLK1 CLK1 0.8V CLK1 0.2V (RxD -RxD CLK1 CLK1 0.8V (at receive) -TxD CLK1 -TxD CLK1 (at transmit) Fig.
  • Page 105 7542 Group ELECTRICAL CHARACTERISTICS 2.7542Group (Extended operating temperature version) Applied to: M37542M4T/M2T-XXXFP/GP, M37542F8TFP/GP Absolute Maximum Ratings (Extended operating temperature version) Table 28 Absolute maximum ratings (Extended operating temperature version) Symbol Parameter Conditions Ratings Unit Power source voltage –0.3 to 6.5...
  • Page 106 7542 Group Recommended Operating Conditions (Extended operating temperature version) Table 29 Recommended operating conditions (1) (Extended operating temperature version) (FLASH ROM version: V = 2.7 to 5.5V, Mask ROM version: V = 2.4 to 5.5 V, V = 0 V, Ta = –40 to 85 °C, unless otherwise noted)
  • Page 107 7542 Group Recommended Operating Conditions (Extended operating temperature version)(continued) Table 30 Recommended operating conditions (2) (Extended operating temperature version) (FLASH ROM version: V = 2.7 to 5.5V, Mask ROM version: V = 2.4 to 5.5 V, V = 0 V, Ta = –40 to 85 °C, unless otherwise noted)
  • Page 108 7542 Group Electrical Characteristics (Extended operating temperature version) Table 31 Electrical characteristics (1) (Extended operating temperature version) (FLASH ROM version: V = 2.7 to 5.5V, Mask ROM version: V = 2.4 to 5.5 V, V = 0 V, Ta = –40 to 85 °C, unless otherwise noted)
  • Page 109 7542 Group Electrical Characteristics (Extended operating temperature version) (continued) Table 32 Electrical characteristics (2) (Extended operating temperature version) (FLASH ROM version: V = 2.7 to 5.5V, Mask ROM version: V = 2.4 to 5.5 V, V = 0 V, Ta = –40 to 85 °C, unless otherwise noted)
  • Page 110 When system is used at low temperature, that V is 3.0 V or more is recommended. Electrical Characteristics of 7542 Group Flash Memory (Extended operating temperature version) Table 34 Electrical Characteristics of 7542 Group Flash Memory (Extended operating temperature version) Limits Test...
  • Page 111 7542 Group Timing Requirements (Extended operating temperature version) Table 35 Timing requirements (1) (Extended operating temperature version) (FLASH ROM version: V = 4.0 to 5.5V, Mask ROM version: V = 4.0 to 5.5 V, V = 0 V, Ta = –40 to 85 °C, unless otherwise noted)
  • Page 112 7542 Group Switching Characteristics (Extended operating temperature version) Table 37 Switching characteristics (1) (Extended operating temperature version) (FLASH ROM version: V = 4.0 to 5.5V, Mask ROM version: V = 4.0 to 5.5 V, V = 0 V, Ta = –40 to 85 °C, unless otherwise noted)
  • Page 113 7542 Group (CNTR (CNTR (CNTR CNTR 0.8V 0.2V (CNTR (CNTR , INT 0.8V 0.2V , CAP (RESET) RESET 0.2V 0.8V 0.2V CLK1 CLK1 CLK1 0.8V CLK1 0.2V (RxD -RxD CLK1 CLK1 0.8V (at receive) -TxD CLK1 -TxD CLK1 (at transmit) Fig.
  • Page 114 7542 Group ELECTRICAL CHARACTERISTICS 3.7542Group (Extended operating temperature 125 °C version) Applied to: M37542M4V/M2V-XXXFP/GP, M37542F8VFP/GP Absolute Maximum Ratings (Extended operating temperature 125 °C version) Table 39 Absolute maximum ratings (Extended operating temperature 125 °C version) Symbol Parameter Conditions Ratings Unit Power source voltage –0.3 to 6.5...
  • Page 115 7542 Group Recommended Operating Conditions (Extended operating temperature 125 °C version) Table 40 Recommended operating conditions (1) (Extended operating temperature 125 °C version) (FLASH ROM version: V = 2.7 to 5.5V, Mask ROM version: V = 2.4 to 5.5 V, V = 0 V, Ta = –40 to 125 °C, unless otherwise noted)
  • Page 116 7542 Group Recommended Operating Conditions (Extended operating temperature 125 °C version)(continued) Table 41 Recommended operating conditions (2) (Extended operating temperature 125 °C version) (FLASH ROM version: V = 2.7 to 5.5V, Mask ROM version: V = 2.4 to 5.5 V, V = 0 V, Ta = –40 to 125 °C, unless otherwise noted)
  • Page 117 7542 Group Electrical Characteristics (Extended operating temperature 125 °C version) Table 42 Electrical characteristics (1) (Extended operating temperature 125 °C version) (FLASH ROM version: V = 2.7 to 5.5V, Mask ROM version: V = 2.4 to 5.5 V, V = 0 V, Ta = –40 to 125 °C, unless otherwise noted)
  • Page 118 7542 Group Electrical Characteristics (Extended operating temperature 125 °C version) (continued) Table 43 Electrical characteristics (2) (Extended operating temperature 125 °C version) (FLASH ROM version: V = 2.7 to 5.5V, Mask ROM version: V = 2.4 to 5.5 V, V = 0 V, Ta = –40 to 125 °C, unless otherwise noted)
  • Page 119 When system is used at low temperature, that V is 3.0 V or more is recommended. Electrical Characteristics of 7542 Group Flash Memory (Extended operating temperature 125 °C version) Table 45 Electrical Characteristics of 7542 Group Flash Memory (Extended operating temperature 125 °C version) Limits Test...
  • Page 120 7542 Group Timing Requirements (Extended operating temperature 125 °C version) Table 46 Timing requirements (1) (Extended operating temperature 125 °C version) (FLASH ROM version: V = 4.0 to 5.5V, Mask ROM version: V = 4.0 to 5.5 V, V = 0 V, Ta = –40 to 125 °C, unless otherwise noted)
  • Page 121 7542 Group Switching Characteristics (Extended operating temperature 125 °C version) Table 48 Switching characteristics (1) (Extended operating temperature 125 °C version) (FLASH ROM version: V = 4.0 to 5.5V, Mask ROM version: V = 4.0 to 5.5 V, V = 0 V, Ta = –40 to 125 °C, unless otherwise noted)
  • Page 122 7542 Group (CNTR (CNTR (CNTR CNTR 0.8V 0.2V (CNTR (CNTR , INT 0.8V 0.2V , CAP (RESET) RESET 0.2V 0.8V 0.2V CLK1 CLK1 CLK1 0.8V CLK1 0.2V (RxD -RxD CLK1 CLK1 0.8V (at receive) -TxD CLK1 -TxD CLK1 (at transmit) Fig.
  • Page 123 7542 Group PACKAGE OUTLINE JEITA Package Code RENESAS Code Previous Code MASS[Typ.] P-LQFP32-7x7-0.80 PLQP0032GB-A 32P6U-A 0.2g NOTE) DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. Dimension in Millimeters Reference Symbol Terminal cross section Index mark 0.32...
  • Page 124 7542 Group JEITA Package Code RENESAS Code Previous Code MASS[Typ.] P-SDIP32-8.9x28-1.78 PRDP0032BA-A 32P4B 2.2g NOTE) DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. Dimension in Millimeters Reference Symbol 9.86 10.16 10.46 27.8 28.0...
  • Page 125 7542 Group APPENDIX 2. Decimal calculations (1) Execution of decimal calculations NOTES ON PROGRAMMING The ADC and SBC are the only instructions which will yield proper decimal notation, set the decimal mode flag (D) to “1” with the 1. Processor Status Register SED instruction.
  • Page 126 7542 Group 4. Notes in stand-by state 5. Read-modify-write instruction In stand-by state* for low-power dissipation, do not make input Do not execute a read-modify-write instruction to the read invalid levels of an input port and an I/O port “undefined”.
  • Page 127 7542 Group Notes on Interrupts 6. Direction register The values of the port direction registers cannot be read. 1. Change of relevant register settings That is, it is impossible to use the LDA instruction, memory opera- When not requiring for the interrupt occurrence synchronous with tion instruction when the T flag is “1”, addressing mode using...
  • Page 128 7542 Group Notes on Timers 3. Interrupt discrimination bit Use an LDM instruction to clear to “0” an interrupt discrimination 1. When n (0 to 255) is written to a timer latch, the frequency divi- bit. sion ratio is 1/(n+1).
  • Page 129 7542 Group Notes on Output Compare Notes on Input Capture 1. When the selected source timer of each compare channel is 1. If the capture trigger is input while the capture register (low-or- stopped, written data to compare register is loaded to the com- der and high-order) is in read, captured value is changed pare latch simultaneously.
  • Page 130 7542 Group Notes on Serial I/Oi (i=1, 2) 3. Notes common to clock synchronous serial I/O and UART 1. Clock synchronous serial I/O (1) Set the serial I/Oi (i=1, 2) control register again after the trans- mission and the reception circuits are reset by clearing both (1) When the transmit operation is stopped, clear the serial I/Oi enable bit and the transmit enable bit to “0”...
  • Page 131 7542 Group Notes on Serial I/O1 Notes on Serial I/O2 1. I/O pin function when serial I/O1 is enabled. 1. I/O pin function when serial I/O2 is enabled The pin functions of P0 and P0 are switched to as The pin functions of P1...
  • Page 132 7542 Group Notes on A/D conversion 6. A/D conversion accuracy 1. Analog input pin As for AD translation accuracy, on the following operating condi- Make the signal source impedance for analog input low, or equip tions, accuracy may become low.
  • Page 133 7542 Group Notes on Clock Generating Circuit 8. External clock When the external signal clock is used for the main clock, connect 1. Switch of ceramic and RC oscillations the X pin to the clock source and leave X pin open.
  • Page 134 7542 Group Electric Characteristic Differences Between Notes on On-chip Oscillation Division Ratio Mask ROM, Flash Memory MCUs • When the clock division ratio is switched from f(X ) to on-chip There are differences in electric characteristics, operation margin, oscillator by the clock division ratio selection bits (bits 7 and 6 of...
  • Page 135 7542 Group Datasheet REVISION HISTORY Rev. Date Description Page Summary – First edition issued 1.00 Nov 27, 2002 FEATURES; Memory size revised. 2.00 Apr 21, 2003 Memory size; Flash memory size revised. Fig.8; ROM size revised. Table 2; ROM size revised.
  • Page 136 7542 Group Datasheet REVISION HISTORY Rev. Date Description Page Summary Information about 36PJW-A package version added. 2.03 Feb 10, 2004 - Fig.4 Pin configuration added. - Fig.9 Functional block diagram added. - Table 1: Notes 2, 3 revised. - 36PJW-A package added.
  • Page 137 7542 Group Datasheet REVISION HISTORY Rev. Date Description Page Summary ROM size of Flash memory version revised. 3.00 Jun 01, 2005 Fig.1 M37542F8GP → M37542FxGP Fig.2 M37542F8FP → M37542FxFP Fig.3 M37542F8SP → M37542FxSP Table 1 Performance overview added. Table 2 Function of Vcc, Vss revised.
  • Page 138 7542 Group Datasheet REVISION HISTORY Rev. Date Description Page Summary Table 3 : ROM size revised and note 2 added. 3.02 Oct 31, 2006 ROM : Description added. Fig. 15 : Note 2 added. Table 7 : X and X added.
  • Page 139 (4) any other purposes that pose a direct threat to human life Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who elect to use Renesas products in any of the foregoing applications shall indemnify and hold harmless Renesas Technology Corp., its affiliated companies and their officers, directors, and employees against any and all...