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7542 Group
I/O Ports
[Direction registers] PiD
The I/O ports have direction registers which determine the input/
output direction of each pin. Each bit in a direction register corre-
sponds to one pin, and each pin can be set to be input or output.
When "1" is set to the bit corresponding to a pin, this pin becomes
an output port. When "0" is set to the bit, the pin becomes an in-
put port.
When data is read from a pin set to output, not the value of the pin
itself but the value of port latch is read. Pins set to input are float-
ing, and permit reading pin values.
If a pin set to input is written to, only the port latch is written to and
the pin remains floating.
Note: P2
/AN
, P2
/AN
, P3
and P3
6
6
7
7
5
and PWQN0036KA-A package.
Accordingly, the following settings are required;
• Select P3
for the INT
3
• Set direction registers of ports P2
• Set direction registers of ports P3
[Port P0P3 drive capacity control register] DCCR
By setting the Port P0P3 drive capacity control register (address
0015
), the drive capacity of the N-channel output transistor for
16
the port P0 and port P3 can be selected.
[Pull-up control register] PULL
By setting the pull-up control register (address 0016
and P3 can exert pull-up control by program. However, pins set to
output are disconnected from this control and cannot exert pull-up
control.
[Port P1P3 control register] P1P3C
By setting the port P1P3 control register (address 0017
CMOS input level or a TTL input level can be selected for ports
P1
, P1
, P1
, P3
, and P3
0
2
3
6
7
Rev.3.02
Oct 31, 2006
REJ03B0006-0302
do not exist for the 32-pin version
6
function.
1
and P2
to output.
6
7
and P3
to output.
5
6
), ports P0
16
by program.
Page 19 of 134
b 7
N o t e : N u m b e r o f L E D d r i v e p o r t ( d r i v e c a p a c i t y i s H I G H ) i s 8 - p o r t .
Fig. 17 Structure of port P0P3 drive capacity control register
b 7
N o t e : P i n s s e t t o o u t p u t p o r t s a r e d i s c o n n e c t e d f r o m p u l l - u p c o n t r o l .
), a
16
Fig. 18 Structure of pull-up control register
b7
Note: Keep setting the P3
to "0" (initial value) for 32-pin version and 36PJW-A package.
Fig. 19 Structure of port P1P3 control register
b 0
P o r t P 0 P 3 d r i v e c a p a c i t y c o n t r o l r e g i s t e r
( D C C R : a d d r e s s 0 0 1 5
, i n i t i a l v a l u e : 0 0
1 6
P o r t P 0
d r i v e c a p a c i t y b i t
0
P o r t s P 0
, P 0
d r i v e c a p a c i t y b i t
1
2
P o r t s P 0
–P 0
d r i v e c a p a c i t y b i t
3
7
P o r t P 3
d r i v e c a p a c i t y b i t
0
P o r t s P 3
P 3
d r i v e c a p a c i t y b i t
1,
2
P o r t P 3
d r i v e c a p a c i t y b i t
3
P o r t s P 3
, P 3
d r i v e c a p a c i t y b i t
4
5
P o r t s P 3
, P 3
d r i v e c a p a c i t y b i t
6
7
0 : L o w
1 : H i g h
b 0
Pull-up control register
(PULL: address 0016
, initial value: 00
16
P 0
p u l l - u p c o n t r o l b i t
0
P 0
, P 0
p u l l - u p c o n t r o l b i t
1
2
P 0
–P 0
p u l l - u p c o n t r o l b i t
3
7
P 3
p u l l - u p c o n t r o l b i t
0
P 3
, P 3
p u l l - u p c o n t r o l b i t
1
2
P 3
p u l l - u p c o n t r o l b i t
3
P 3
, P 3
p u l l - u p c o n t r o l b i t
4
5
P 3
, P 3
p u l l - u p c o n t r o l b i t
6
7
b0
Port P1P3 control register
(P1P3C: address 0017
16
P3
/INT
input level selection bit
7
0
0 : CMOS level
1 : TTL level
P3
/INT
input level selection bit
6
1
0 : CMOS level
1 : TTL level
P1
,P1
,P1
input level selection bit
0
2
3
0 : CMOS level
1 : TTL level
Not used
/INT
input level selection bit
6
1
)
1 6
)
16
0 : P u l l - u p O f f
1 : P u l l - u p O n
, initial value: 00
)
16
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