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7542 Group
Software Commands
Table 11 lists the software commands.
After setting the CPU rewrite mode select bit to "1", execute a soft-
ware command to specify an erase or program operation.
Each software command is explained below.
• Read Array Command (FF
The read array mode is entered by writing the command code
"FF
" in the first bus cycle. When an address to be read is input
16
in one of the bus cycles that follow, the contents of the specified
address are read out at the data bus (D
The read array mode is retained until another command is written.
• Read Status Register Command (70
When the command code "70
the contents of the status register are read out at the data bus (D
to D
) by a read in the second bus cycle.
7
The status register is explained in the next section.
• Clear Status Register Command (50
This command is used to clear the bits SR4 and SR5 of the status
register after they have been set. These bits indicate that opera-
tion has ended in an error. To use this command, write the
command code "50
" in the first bus cycle.
16
• Program Command (40
16
Program operation starts when the command code "40
ten in the first bus cycle. Then, if the address and data to program
are written in the 2nd bus cycle, program operation (data program-
ming and verification) will start.
Whether the write operation is completed can be confirmed by
read status register or the RY/BY status flag. When the program
starts, the read status register mode is entered automatically and
the contents of the status register is read at the data bus (D
D
). The status register bit 7 (SR7) is set to "0" at the same time
7
the write operation starts and is returned to "1" upon completion of
the write operation. In this case, the read status register mode re-
mains active until the read array command (FF
Table 11 List of software commands (CPU rewrite mode)
Command
Read array
Read status register
Clear status register
Program
Block erase
SRD = Status Register Data
WA = Write Address, WD = Write Data
BA = Block Address to be erased (Input the maximum address of each block.)
=
denotes a given address in the user ROM area.
Rev.3.02
Oct 31, 2006
REJ03B0006-0302
)
16
to D
).
0
7
)
16
" is written in the first bus cycle,
16
)
16
)
16
_____
) is written.
16
Mode
Write
Write
Write
Write
Write
Page 77 of 134
The RY/BY status flag of the flash memory control register is "0"
during write operation and "1" when the write operation is com-
pleted as is the status register bit 7.
At program end, program results can be checked by reading the
status register.
Write "40
Write address
Write
Write data
0
Read status register
RY/BY = "1" ?
SR4 = "0"?
" is writ-
Program
completed
to
0
Fig. 99 Program flowchart
First bus cycle
Data
Address
(D
to D
0
(Note 4)
FF
16
70
16
50
16
40
16
20
16
Start
"
16
SR7 = "1"?
NO
or
YES
NO
YES
Second bus cycle
Mode
Address
)
7
Read
WA (Note 2)
Write
BA (Note 3)
Write
Program
error
Data
(D
to D
)
0
7
SRD (Note 1)
WD (Note 2)
D0
16
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