Advertisement
7542 Group
Timing Requirements (Extended operating temperature version)
Table 35 Timing requirements (1) (Extended operating temperature version)
(FLASH ROM version: V
CC
Symbol
t
(RESET)
Reset input "L" pulse width
W
t
(X
)
External clock input cycle time
C
IN
t
(X
)
External clock input "H" pulse width
WH
IN
t
(X
)
External clock input "L" pulse width
WL
IN
t
(CNTR
)
CNTR
C
0
t
(CNTR
)
CNTR
WH
0
t
(CNTR
)
CNTR
WL
0
t
(S
)
Serial I/O1, serial I/O2 clock input cycle time (Note 2)
C
CLK1
t
(S
)
Serial I/O1, serial I/O2 clock input "H" pulse width (Note 2)
WH
CLK1
t
(S
)
Serial I/O1, serial I/O2 clock input "L" pulse width (Note 2)
WL
CLK1
t
(RxD
–S
)
Serial I/O1, serial I/O2 input set up time
su
1
CLK1
t
(S
–RxD
)
Serial I/O1, serial I/O2 input hold time
h
CLK1
1
Notes 1: As for CAP
, CAP
, it is the value when noise filter is not used.
0
1
2: In this time, bit 6 of the serial I/O1 control register (address 001A
When bit 6 of the serial I/O1 control register is "0" (clock asynchronous serial I/O is selected), the rating values are divided by 4.
In this time, bit 6 of the serial I/O2 control register (address 0030
When bit 6 of the serial I/O2 control register is "0" (clock asynchronous serial I/O is selected), the rating values are divided by 4.
Table 36 Timing requirements (2) (Extended operating temperature version)
(FLASH ROM version: V
CC
Symbol
t
(RESET)
Reset input "L" pulse width
W
t
(X
)
External clock input cycle time
C
IN
t
(X
)
External clock input "H" pulse width
WH
IN
t
(X
)
External clock input "L" pulse width
WL
IN
t
(CNTR
)
CNTR
C
0
t
(CNTR
)
CNTR
WH
0
t
(CNTR
)
CNTR
WL
0
t
(S
)
Serial I/O1, serial I/O2 clock input cycle time (Note 2)
C
CLK1
t
(S
)
Serial I/O1, serial I/O2 clock input "H" pulse width (Note 2)
WH
CLK1
t
(S
)
Serial I/O1, serial I/O2 clock input "L" pulse width (Note 2)
WL
CLK1
t
(RxD
–S
)
Serial I/O1, serial I/O2 input set up time
su
1
CLK1
t
(S
–RxD
)
Serial I/O1, serial I/O2 input hold time
h
CLK1
1
Notes 1: As for CAP
, CAP
, it is the value when noise filter is not used.
0
1
2: In this time, bit 6 of the serial I/O1 control register (address 001A
When bit 6 of the serial I/O1 control register is "0" (clock asynchronous serial I/O1 is selected), the rating values are divided by 4.
In this time, bit 6 of the serial I/O2 control register (address 0030
When bit 6 of the serial I/O2 control register is "0" (clock asynchronous serial I/O is selected), the rating values are divided by 4.
Rev.3.02
Oct 31, 2006
REJ03B0006-0302
= 4.0 to 5.5V, Mask ROM version: V
Parameter
input cycle time
0
, INT
, INT
, CAP
, CAP
0
0
1
0
1
, INT
, INT
, CAP
, CAP
0
0
1
0
1
= 2.7 to 5.5V, Mask ROM version: V
Parameter
input cycle time
0
, INT
, INT
, CAP
, CAP
0
0
1
0
1
, INT
, INT
, CAP
, CAP
0
0
1
0
1
Page 111 of 134
= 4.0 to 5.5 V, V
CC
SS
input "H" pulse width (Note 1)
input "L" pulse width (Note 1)
) is set to "1" (clock synchronous serial I/O is selected).
16
) is set to "1" (clock synchronous serial I/O is selected).
16
= 2.4 to 5.5 V, V
CC
SS
input "H" pulse width (Note 1)
input "L" pulse width (Note 1)
) is set to "1" (clock synchronous serial I/O is selected).
16
) is set to "1" (clock synchronous serial I/O is selected).
16
= 0 V, Ta = –40 to 85 °C, unless otherwise noted)
Limits
Min.
Typ.
2
125
50
50
200
80
80
800
370
370
220
100
= 0 V, Ta = –40 to 85 °C, unless otherwise noted)
Limits
Min.
Typ.
2
250
100
100
500
230
230
2000
950
950
400
200
Unit
Max.
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Unit
Max.
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Advertisement
