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7542 Group
Table 24 Timing requirements (3) (General purpose)
(Mask ROM version: V
= 2.2 to 5.5 V, V
CC
Symbol
t
(RESET)
Reset input "L" pulse width
W
t
(X
)
External clock input cycle time
C
IN
t
(X
)
External clock input "H" pulse width
WH
IN
t
(X
)
External clock input "L" pulse width
WL
IN
t
(CNTR
)
CNTR
C
0
t
(CNTR
)
CNTR
WH
0
t
(CNTR
)
CNTR
WL
0
t
(S
)
Serial I/O1, serial I/O2 clock input cycle time (Note 2)
C
CLK1
t
(S
)
Serial I/O1, serial I/O2 clock input "H" pulse width (Note 2)
WH
CLK1
t
(S
)
Serial I/O1, serial I/O2 clock input "L" pulse width (Note 2)
WL
CLK1
t
(RxD
–S
)
Serial I/O1, serial I/O2 input set up time
su
1
CLK1
t
(S
–RxD
)
Serial I/O1, serial I/O2 input hold time
h
CLK1
1
Notes 1: As for CAP
, CAP
, it is the value when noise filter is not used.
0
1
2: In this time, bit 6 of the serial I/O1 control register (address 001A
When bit 6 of the serial I/O1 control register is "0" (clock asynchronous serial I/O1 is selected), the rating values are divided by 4.
In this time, bit 6 of the serial I/O2 control register (address 0030
When bit 6 of the serial I/O2 control register is "0" (clock asynchronous serial I/O is selected), the rating values are divided by 4.
Rev.3.02
Oct 31, 2006
REJ03B0006-0302
= 0 V, Ta = –20 to 85 °C, unless otherwise noted) (This is only for the mask ROM version.)
SS
Parameter
input cycle time
0
, INT
, INT
, CAP
, CAP
input "H" pulse width (Note 1)
0
0
1
0
1
, INT
, INT
, CAP
, CAP
input "L" pulse width (Note 1)
0
0
1
0
1
Page 102 of 134
) is set to "1" (clock synchronous serial I/O is selected).
16
) is set to "1" (clock synchronous serial I/O is selected).
16
Limits
Min.
Typ.
Max.
2
500
200
200
1000
460
460
4000
1900
1900
800
400
Unit
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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