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7542 Group
Notes on Output Compare
1. When the selected source timer of each compare channel is
stopped, written data to compare register is loaded to the com-
pare latch simultaneously.
2. Do not write the same data to both of compare latch x0 (x=0, 1,
2, 3) and x1.
3. When setting value of the compare register is larger than timer
setting value, compare match signal is not generated. Accord-
ingly, the output waveform is fixed to "L" or "H" level.
However, when setting value of another compare register is
smaller than timer setting value, this compare match signal is
generated. Accordingly, if the corresponding compare latch y
(y=00, 01, 10, 11, 20, 21, 30, 31) interrupt source bit is set to "1"
(valid), compare match interrupt request occurs.
4. When the compare x trigger enable bit is cleared to "0" (dis-
abled), the match trigger to the waveform output circuit is
disabled. Accordingly, the output waveform can be fixed to "L"
or "H" level.
However, in this case, the compare match signal is generated.
Accordingly, if the corresponding compare latch y (y=00, 01, 10,
11, 20, 21, 30, 31) interrupt source bit is set to "1"
(valid),compare match interrupt request occurs.
Rev.3.02
Oct 31, 2006
REJ03B0006-0302
Page 129 of 134
Notes on Input Capture
1. If the capture trigger is input while the capture register (low-or-
der and high-order) is in read, captured value is changed
between high-order reading and low-order reading. Accordingly,
some countermeasure by software is recommended, for ex-
ample comparing the values that twice of read.
2. Timer A cannot be used for the capture source timer in the fol-
lowing state;
• X
oscillation selected by clock division ratio selection bits
IN
(bits 7 and 6 of CPU mode register (address 3B
• Timer A count source: On-chip oscillator output.
Timer B cannot be used for the capture source timer in the fol-
lowing state;
• X
oscillation selected by clock division ratio selection bits
IN
• Timer B count source: Timer A underflow
• Timer A count source: On-chip oscillator output.
3. As shown below, when the capture input is performed to both
capture latch 00 and 01 at the same time, the value of capture
0 status bit (bit 4 of capture/compare status register (address
22
)) is undefined (same as capture 1).
16
• When "1" is written to capture latch 00 software trigger bit (bit 0
of capture software trigger register (address 13
latch 01 software trigger bit (bit 1 of capture software trigger reg-
ister) at the same time
• When external trigger of capture latch 00 and software trigger of
capture latch 01 occur at the same time
• When external trigger of capture latch 01 and software trigger of
capture latch 00 occur at the same time
4. When the capture interrupt is used as the interrupt for return
from stop mode, set the capture 0 noise filter clock selection
bits (bits 5 and 4 of capture mode register (address 20
"00 (Filter stop)" (same as capture 1).
))
16
)) and capture
16
)) to
16
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