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7542 Group
6. Direction register
The values of the port direction registers cannot be read.
That is, it is impossible to use the LDA instruction, memory opera-
tion instruction when the T flag is "1", addressing mode using
direction register values as qualifiers, and bit test instructions such
as BBC and BBS.
It is also impossible to use bit operation instructions such as CLB
and SEB and read-modify-write instructions of direction registers
for calculations such as ROR.
For setting direction registers, use the LDM instruction, STA in-
struction, etc.
Termination of Unused Pins
1. Terminate unused pins
Perform the following wiring at the shortest possible distance (20
mm or less) from microcomputer pins.
(1) I/O ports
Set the I/O ports for the input mode and connect each pin to V
or V
through each resistor of 1 kΩ to 10 kΩ. The port which can
SS
select a built-in pull-up resistor can also use the built-in pull-up re-
sistor.
When using the I/O ports as the output mode, open them at "L" or
"H".
• When opening them in the output mode, the input mode of the
initial status remains until the mode of the ports is switched over
to the output mode by the program after reset. Thus, the poten-
tial at these pins is undefined and the power source current may
increase in the input mode. With regard to an effects on the sys-
tem, thoroughly perform system evaluation on the user side.
• Since the direction register setup may be changed because of a
program runaway or noise, set direction registers by program
periodically to increase the reliability of program.
2. Termination remarks
(1) I/O ports setting as input mode
[1] Do not open in the input mode.
<Reason>
• The power source current may increase depending on the first-
stage circuit.
• An effect due to noise may be easily produced as compared with
proper termination (1) shown on the above "1. Terminate unused
pins".
[2] Do not connect to V
or V
CC
<Reason>
If the direction register setup changes for the output mode be-
cause of a program runaway or noise, a short circuit may occur.
[3] Do not connect multiple ports in a lump to V
a resistor.
<Reason>
If the direction register setup changes for the output mode be-
cause of a program runaway or noise, a short circuit may occur
between ports.
Rev.3.02
Oct 31, 2006
REJ03B0006-0302
directly.
SS
or V
through
CC
SS
Page 127 of 134
Notes on Interrupts
1. Change of relevant register settings
When not requiring for the interrupt occurrence synchronous with
the following case, take the sequence shown in Figure 4.
• When switching external interrupt active edge
• When switching interrupt sources of an interrupt vector address
where two or more interrupt sources are allocated
Set the corresponding interrupt enable bit to "0" (disabled) .
Set the interrupt edge selection bit, active edge switch bit, or
the interrupt source selection bit.
NOP (One or more instructions)
Set the corresponding interrupt request bit to "0"
(no interrupt request issued).
CC
Set the corresponding interrupt enable bit to "1" (enabled).
Fig. 4 Sequence of changing relevant register
<Reason>
When setting the followings, the interrupt request bit of the corre-
sponding interrupt may be set to "1".
• When switching external interrupt active edge
INT
interrupt edge selection bit
0
(bit 0 of Interrupt edge selection register (address 3A
INT
interrupt edge selection bit
1
(bit 1 of Interrupt edge selection register)
CNTR
active edge switch bit
0
(bit 2 of timer X mode register (address 2B
Capture 0 interrupt edge selection bit
(bits 1 and 0 of capture mode register (address 20
Capture 1 interrupt edge selection bit
(bits 3 and 2 of capture mode register)
2. Check of interrupt request bit
When executing the BBC or BBS instruction to determine an in-
terrupt request bit immediately after this bit is set to "0", take the
following sequence.
<Reason>
If the BBC or BBS instruction is executed immediately after an in-
terrupt request bit is cleared to "0", the value of the interrupt
request bit before being cleared to "0" is read.
Set the interrupt request bit to "0" (no interrupt issued)
NOP (one or more instructions)
Execute the BBC or BBS instruction
Fig. 5 Sequence of check of interrupt request bit
↓
↓
↓
↓
))
16
))
16
))
16
↓
↓
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