Renesas 7542 Manual page 22

7542 Group
(8) Port P1
0
Serial I/O1 enable bit
Receive enable bit
Direction
register
Data bus Port latch
Serial I/O1 input
Capture 0 input control
Capture 0 input
(10) Port P1
2
Serial I/O1 synchronous
clock selection bit
Serial I/O1 enable bit
Serial I/O1 mode selection bit
Serial I/O1 enable bit
Direction
register
Data bus
Port latch
Serial I/O1 clock output
(12) Port P1
4
Pulse output mode
Direction
register
Port latch
Data bus
Timer output
P1 , P1 , P1 , P3 , and P3
0 2 3 6
*
When the TTL level is selected, there is no hysteresis characteristics.
Fig. 21 Block diagram of ports (2)
Rev.3.02 Oct 31, 2006
REJ03B0006-0302
P1 , P1 , P1
0 2 3
input level
selection bit
*
P1
0
input level
selection bit
Serial I/O1 clock input
CNTR interrupt input
0
input level are switched to the CMOS/TTL level by the port P1P3 control register.
7
Page 22 of 134
(9) Port P1
1
P1 /T D P-channel output disable bit
1 x 1
Serial I/O1 enable bit
Transmit enable bit
Direction
register
Data bus
Port latch
Serial I/O1 output
(11) Port P1
3
Serial I/O1 mode selection bit
Serial I/O1 enable bit
S output enable bit
RDY1
Data bus
, P1 , P1
2 3
Serial I/O1 ready output
*
(13) Ports P2 –P2
0
Data bus
Direction
register
Port latch
7
Direction
register
Port latch
A/D converter input
Analog input pin
selection bit
P1 , P1 , P1
0 2 3
input level
selection bit
*