Check The Setup/Hold With Single Clock Edges, Multiple Clocks - Agilent Technologies 1670G Series Service Manual

Testing Performance
To test the multiple-clock, multiple-edge, state acquisition (logic analyzer)

Check the setup/hold with single clock edges, multiple clocks

Select the logic analyzer setup/hold time.
1
a In the logic analyzer Format menu, select Master Clock.
b Select and activate any two clock edges.
c Select the Setup/Hold field and select the setup/hold to be tested for all pods. The first
time through this test, use the top combination in the following table.
Setup/Hold Combinations
4.0/0.0 ns
-0.5/4.5 ns
d Select Done to exit the setup/hold combinations.
Disable the pulse generator channel 1 COMP (with the LED off).
2
Using the Delay mode of the pulse generator channel 1, position the pulses
3
according to the setup time of the setup/hold combination selected, +0.0 ps or
−100 ps.
a On the Oscilloscope, select [Define meas] Define ∆ Time - Stop edge: rising.
b In the oscilloscope timebase menu, select Position. Using the oscilloscope knob,
position the rising edge of the clock waveform so that it is centered on the display.
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