Test The Next Channels - Agilent Technologies 1670G Series Service Manual

Testing Performance
To test the single-clock, multiple-edge, state acquisition (logic analyzer)
Test the next setup/hold combination.
7
a In the logic analyzer Format menu, select Master Clock.
b Turn off and disconnect the clock just tested.
c Repeat steps 1 through 10 for the next setup/hold combination listed in step 1 on
page 3–48, until all listed setup/hold combinations have been tested.
When aligning the data and clock waveforms using the oscilloscope, align the waveforms
according to the setup time of the setup/hold combination being tested, +0.0 ps or −100 ps.

Test the next channels

•
Connect the next combination of data channels and clock channels, then test them.
Start on page 3–44, "Connect the logic analyzer," connect the next combination, then continue
through the complete test.
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