Testing Performance
To test the single-clock, single-edge, state acquisition (logic analyzer)
Check the setup/hold combination
Select the logic analyzer setup/hold time.
1
a In the logic analyzer Format menu, select Master Clock.
b Select the Setup/Hold field, then select the setup/hold combination to be tested for all
pods. The first time through this test, use the top combination in the following table.
Setup/Hold Combinations
3.0/0.0 ns
-0.5/3.5 ns
c Select Done to exit the setup/hold combinations.
Disable the pulse generator channel 1 COMP (with the LED off).
2
Using the Delay mode of the pulse generator channel 1, position the pulses
3
according to the setup time of the setup/hold combination selected, +0.0 ps or
−100 ps.
a On the Oscilloscope, select [Define meas] Define ∆ Time - Stop edge: rising.
b In the oscilloscope timebase menu, select Position. Using the oscilloscope knob,
position the rising edge of the clock waveform so that it is centered on the display.
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