Agilent Technologies 1670G Series Service Manual page 213

Theory of Operation
Analyzer Tests (Analy PV)
Passing the PLD Test implies that the PLD is not corrupted and that data can be passed
between the acquisition board and the CPU board.
Oscillator Test The Oscillator Test functionally verifies the two oscillators and the
oscillator internal pathways on the logic analyzer module. The oscillators are checked
using the event counter on one of the acquisition ICs. The event counter will count the
number of oscillator periods within a pre-determined time window. The count of
oscillator periods is then compared with a known value.
Passing the Oscillator Test implies that both oscillators on the logic analyzer module are
operating properly.
Data Memory Test After verifying the integrity of the memory address bus, the
acquisition RAM is checked by filling the RAM with a checkerboard pattern of "1"s and
"0"s then reading each memory location and comparing the test pattern with known
values. Then the RAM is filled with an inverse checkerboard pattern, read, and compared
with known values. The acquisition ICs are then used to generate a walking "1"s pattern,
which is stored in RAM. The patterns are then read and compared with known values.
Passing the memory test implies that the acquisition RAM is functioning and that each
memory location bit can hold either a logic "1" or logic "0." Passing this test also implies that
the RAM is addressable by both the acquisition ICs and the mainframe CPU system through
the CPU interface.
Alignment Test The alignment test exercises the clock optimization circuit on-board
the acquisition IC. A test signal is generated by the comparators and sent to the
acquisition IC. A test run is then done to see if the clock optimization circuit aligns the
data signal with the master clock signal.
Passing the alignment test implies the clock optimization circuit that resides on the
acquisition IC operates properly. Consequently the acquisition IC can properly sample data
with minimal channel-to-channel skew.
Comparators Test The comparators in the logic analyzer front end are checked by
varying the threshold voltage and reading the state of the activity indicators. The output
of the comparator DAC is set to the upper voltage limit and the activity indicators for all
the pod channels are read to see if they are all in a low state.
The DAC output is then set to the lower voltage limit, and the activity indicators are read to
see if they are in a high state. The DAC output is then set to 0.0 V, allowing the comparators
to recognize the test signal being routed to the test input pin of all of the comparators.
Consequently, the activity indicators are read to see if they show activity on all channels of all
the pods.
If the Comparators Test reveals that a logic analyzer channel is not recognizing the test data, a
message will appear alerting the user that the channel is not operating as expected. If the
module cannot be immediately serviced, then the user is alerted so that the failed channel is
not used until the module can be serviced.
Passing the Comparators Test implies that the logic analyzer front end is operating properly
and all channels are capable of passing data to the acquisition ICs.
Acquisition IC Verification Tests
During the Acquisition IC Verification Tests, five tests are performed on the acquisition ICs.
The tests are the Communications, Encoder, Resource, Sequencer, and Clock Tests.
Communication Test The communication test verifies that communications pipeline
between the various subsystems of the IC are operating. Checkerboard patterns of "1"s
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