Agilent Technologies 1670G Series Service Manual page 214

Theory of Operation
Analyzer Tests (Analy PV)
and "0"s are routed to the address and data buses and to the read/write registers of each
chip. After verifying the communications pipelines, the acquisition clock synchronization
signals that are routed from IC to IC are checked. Finally, the IC master clock
optimization path is checked and verified.
Passing the communication test implies that the communications pipelines running from
subsystem to subsystem on the acquisition IC are functioning and that the clock optimization
circuit on the IC is functioning. Also, passing this test implies that the acquisition clock
synchronization signals are functioning and appear at the synchronization signal output pins
of the acquisition IC.
Encoder Test The encoder is tested and verified using a walking "1" and walking "0"
pattern. The walking "1" and "0" is used to stimulate all of the encoder output pins which
connect directly to the memory ICs. Additionally, the post-store counter in each of the
acquisition ICs is tested.
Passing the encoder test implies that the encoder is functioning and can properly route the
acquired data to the acquisition memory. Also, passing this test implies that the post-store
counter on the acquisition ICs is functioning.
Resource Test The pattern, range, edge, and glitch recognizers are tested and verified.
First, an on-chip test register is verified for correct operation. Next, the pattern
comparators are tested to ensure that each bit in the recognizer as well as the logic
driver/receiver are operating. The edge and glitch pattern detectors are then verified in a
similar manner. The range detectors are verified with their combinational logic to ensure
that the in- and out-of-range conditions are recognized.
Passing the resource test implies that all of the pattern, range, edge, and glitch resources are
operating and that an occurrence of the pattern, edge, or glitch of interest is recognized.
Also, passing this test implies that the range recognizers will detect and report in- and
out-of-range acquisition data to the sequencer or storage qualifier. The drivers and receivers
at the recognizer input and output pins of the acquisition IC are also checked to be sure they
are functioning.
Sequencer Test The sequencer, the state machine that controls acquisition storage, is
tested by first verifying that all of the sequencer registers are operating. After the
registers are checked, the combinational logic of the storage qualification is verified.
Then, both the occurrence counter and the sequencer level counter is checked.
Passing the sequencer test implies that all 12 available sequence levels are functioning and
that all possible sequence level jumps can occur. Also, passing this test implies that
user-defined ANDing and ORing of storage qualified data patterns will occur, and that the
occurrence counter that appears at each sequence level is functioning.
Chip Clock Test The sample clock generator on the acquisition ICs are tested by first
checking the operation of the clock optimization circuit. The state acquisition clock paths
are then checked to ensure that each state clock and clock qualifier are operating by
themselves and in all possible clock and qualifier combinations. The timing acquisition
optimization circuit is then operationally verified. Finally, the timing acquisition
frequency divider (for slower timing sample rates) is checked.
Passing the chip clock test implies that each acquisition IC can generate its own master clock
whether the clock is generated using a combination of external clocking signals (state mode)
or internal sample clock signals (timing mode).
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