NEC V850E/IA1 mPD703116 User Manual page 812

Mnemonic Operands
r r r r r 0 0 0 0 1 1 1 d d d d adr ← ep + zero-extend (disp5)
SLD.HU disp5[ep],
reg2
r r r r r 1 0 1 0 d d d d d d 0 adr ← ep + zero-extend (disp8)
SLD.W disp8[ep],
reg2
r r r r r 0 1 1 1 d d d d d d d adr ← ep + zero-extend (disp7)
SST.B reg2,
disp7[ep]
r r r r r 1 0 0 1 d d d d d d d adr ← ep + zero-extend (disp8)
SST.H reg2,
disp8[ep]
r r r r r 1 0 1 0 d d d d d d 1 adr ← ep + zero-extend (disp8)
SST.W reg2,
disp8[ep]
ST.B reg2, disp16
r r r r r 1 1 1 0 1 0 R R R R R
[reg1]
d d d d d d d d d d d d d d d d
ST.H reg2, disp16 r r r r r 1 1 1 0 1 1 R R R R R
[reg1]
d d d d d d d d d d d d d d d 0
ST.W reg2, disp16
r r r r r 1 1 1 0 1 1 R R R R R
[reg1]
d d d d d d d d d d d d d d d 1
STSR regID, reg2
r r r r r 1 1 1 1 1 1 R R R R R
0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0
r r r r r 0 0 1 1 0 1 R R R R R GR[reg2] ← GR[reg2] − GR[reg1]
SUB reg1, reg2
r r r r r 0 0 1 1 0 0 R R R R R GR[reg2] ← GR[reg1] − GR[reg2]
SUBR reg1, reg2
0 0 0 0 0 0 0 0 0 1 0 R R R R R adr ← (PC + 2) + (GR[reg1] logically shift left by 1)
SWITCH reg1
0 0 0 0 0 0 0 0 1 0 1 R R R R R GR[reg1] ← sign-extend (GR[reg1] (7:0))
SXB reg1
0 0 0 0 0 0 0 0 1 1 1 R R R R R GR[reg1] ← sign-extend (GR[reg1] (15:0))
SXH reg1
TRAP vector
0 0 0 0 0 1 1 1 1 1 1 i i i i i
0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0
r r r r r 0 0 1 0 1 1 R R R R R result ← GR[reg2] AND GR[reg1]
TST reg1, reg2
TST1 bit#3, disp16
1 1 b b b 1 1 1 1 1 0 R R R R R
[reg1]
d d d d d d d d d d d d d d d d
reg2, [reg1]
r r r r r 1 1 1 1 1 1 R R R R R
0 0 0 0 0 0 0 0 1 1 1 0 0 1 1 0
r r r r r 0 0 1 0 0 1 R R R R R GR[reg2] ← GR[reg2] XOR GR[reg1]
XOR reg1, reg2
XORI imm16, reg1,
r r r r r 1 1 0 1 0 1 R R R R R
reg2
i i i i i i i i i i i i i i i i
0 0 0 0 0 0 0 0 1 0 0 R R R R R GR[reg1] ← zero-extend (GR[reg1] (7:0))
ZXB reg1
0 0 0 0 0 0 0 0 1 1 0 R R R R R GR[reg1] ← zero-extend (GR[reg1] (15:0))
ZXH reg1
812
APPENDIX C INSTRUCTION SET LIST
Opcode
GR[reg2] ← zero-extend (Load-memory (adr,
Notes 18, 20
Halfword))
GR[reg2] ← Load-memory (adr, Word)
Note 21
Store-memory (adr, GR[reg2], Byte)
Note 19 Store-memory (adr, GR[reg2], Halfword)
Note 21 Store-memory (adr, GR[reg2], Word)
adr ← GR[reg1] + sign-extend (disp16)
Store-memory (adr, GR[reg2], Byte)
adr ← GR[reg1] + sign-extend (disp16)
Store-memory (adr, GR[reg2], Halfword)
Note 8
adr ← GR[reg1] + sign-extend (disp16)
Store-memory (adr, GR[reg2], Word)
Note 8
GR[reg2] ← SR[regID]
PC ← (PC + 2) + (sign-extend
(Load-memory (adr, Halfword))) logically shift left by 1
← PC + 4 (return PC)
EIPC
← PSW
EIPSW
ECR.EICC ← interrupt code
PSW.EP ← 1
PSW.ID ← 1
PC ← 00000040H (when vector is 00H to 0FH)
00000050H (when vector is 10H to 1FH)
adr ← GR[reg1] + sign-extend (disp16)
Z flag ← Not (Load-memory-bit (adr, bit#3))
adr ← GR[reg1]
Z flag ← Not (Load-memory-bit (adr, reg2))
GR[reg2] ← GR[reg1] XOR zero-extend (imm16)
User's Manual U14492EJ3V0UD
Operation Execution Clock
i
1
1
1
1
1
1
1
1
1
1
1
5
1
1
4
1
3
Note 3
3
Note 3
1
1
1
1
Flags
r I CY OV S Z
1 Note 9
1 Note 9
1 1
1 1
1 1
1 1
1 1
1 1
1 1
× × × ×
1 1
× × × ×
1 1
5 5
1 1
1 1
4 4
× ×
1 1 0
×
3 3
Note 3 Note 3
×
3 3
Note 3 Note 3
× ×
1 1 0
× ×
1 1 0
1 1
1 1
(5/5)
SAT