NEC V850E/IA1 mPD703116 User Manual page 810

Mnemonic Operands
LD.W disp16[reg1],
r r r r r 1 1 1 0 0 1 R R R R R
reg2 d d d d d d d d d d d d d d d 1
r r r r r 0 0 0 0 0 0 R R R R R GR[reg2] ← GR[reg1]
MOV reg1, reg2
r r r r r 0 1 0 0 0 0 i i i i i GR[reg2] ← sign-extend (imm5)
imm5, reg2
0 0 0 0 0 1 1 0 0 0 1 R R R R R GR[reg1] ← imm32
imm32, reg1
i i i i i i i i i i i i i i i i
I I I I I I I I I I I I I I I I
MOVEA imm16, reg1, r r r r r 1 1 0 0 0 1 R R R R R
reg2
i i i i i i i i i i i i i i i i
MOVHI imm16, reg1,
r r r r r 1 1 0 0 1 0 R R R R R
reg2
i i i i i i i i i i i i i i i i
MUL reg1, reg2, r r r r r 1 1 1 1 1 1 R R R R R
reg3 w w w w w 0 1 0 0 0 1 0 0 0 0 0
imm9, reg2, r r r r r 1 1 1 1 1 1 i i i i i
reg3
w w w w w 0 1 0 0 1 I I I I 0 0
r r r r r 0 0 0 1 1 1 R R R R R GR[reg2] ← GR[reg2]
MULH reg1, reg2
r r r r r 0 1 0 1 1 1 i i i i i GR[reg2] ← GR[reg2]
imm5, reg2
MULHI imm16, reg1,
r r r r r 1 1 0 1 1 1 R R R R R
reg2
i i i i i i i i i i i i i i i i
MULU reg1, reg2,
r r r r r 1 1 1 1 1 1 R R R R R
reg3
w w w w w 0 1 0 0 0 1 0 0 0 1 0
imm9, reg2, r r r r r 1 1 1 1 1 1 i i i i i
reg3 w w w w w 0 1 0 0 1 I I I I 1 0
NOP 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Passes at least 1 cycle doing nothing.
r r r r r 0 0 0 0 0 1 R R R R R GR[reg2] ← NOT (GR[reg1])
NOT reg1, reg2
NOT1 bit#3, 0 1 b b b 1 1 1 1 1 0 R R R R R
disp16[reg1] d d d d d d d d d d d d d d d d
reg2, [reg1]
r r r r r 1 1 1 1 1 1 R R R R R
0 0 0 0 0 0 0 0 1 1 1 0 0 0 1 0
r r r r r 0 0 1 0 0 0 R R R R R GR[reg2] ← GR[reg2] OR GR[reg1]
OR reg1, reg2
ORI imm16, reg1,
r r r r r 1 1 0 1 0 0 R R R R R
reg2
i i i i i i i i i i i i i i i i
PREPARE list12, imm5
0 0 0 0 0 1 1 1 1 0 i i i i i L
L L L L L L L L L L L 0 0 0 0 1
list12, imm5,
0 0 0 0 0 1 1 1 1 0 i i i i i L
Note 15
sp/imm
L L L L L L L L L L L f f 0 1 1
imm16/imm32
810
APPENDIX C INSTRUCTION SET LIST
Opcode
adr ← GR[reg1] + sign-extend (disp16)
GR[reg2] ← Load-memory (adr, Word)
Note 8
GR[reg2] ← GR[reg1] + sign-extend (imm16)
GR[reg2] ← GR[reg1] + (imm16 || 0
GR[reg3] || GR[reg2] ← GR[reg2]
reg1 ≠ reg2 ≠ reg3, reg3 ≠ r0
GR[reg3] || GR[reg2] ← GR[reg2]
(imm9)
Note 13
GR[reg2] ← GR[reg1]
GR[reg3] || GR[reg2] ← GR[reg2]
reg1 ≠ reg2 ≠ reg3, reg3 ≠ r0
GR[reg3] || GR[reg2] ← GR[reg2]
(imm9)
Note 13
adr ← GR[reg1] + sign-extend (disp16)
Z flag ← Not (Load-memory-bit (adr, bit#3))
Store-memory-bit (adr, bit#3, Z flag)
adr ← GR[reg1]
Z flag ← Not (Load-memory-bit (adr, reg2))
Store-memory-bit (adr, reg2, Z flag)
GR[reg2] ← GR[reg1] OR zero-extend (imm16)
Store-memory (sp−4, GR[reg in list12], Word)
sp ← sp−4
repeat 1 steps above until regs in list12 is stored
sp ← sp-zero-extend (imm5)
Store-memory (sp−4, GR[reg in list12], Word)
GR[reg in list12] ← Load-memory (sp, Word)
sp ← sp + 4
repeat 2 steps above until regs in list12 is loaded
Note 16
PC ← GR[reg1]
User's Manual U14492EJ3V0UD
Operation Execution Clock
i
1
1
1
2
1
16
)
1
×
GR[reg1]
1
×
sign-extend
1
×
Note 6 Note 6
GR[reg1]
1
×
Note 6
sign-extend (imm5)
1
×
Note 6
imm16
1
×
GR[reg1]
1
×
zero-extend
1
1
1
3
Note 3
3
Note 3
1
1
n+1
Note 4
n+2
Note 4
Note 17
Flags
r I CY OV S Z
1 Note 11
1 1
1 1
2 2
1 1
1 1
2 2
Note 14
2 2
Note 14
1 2
1 2
1 2
2 2
Note 14
2 2
Note 14
1 1
× ×
1 1 0
×
3 3
Note 3 Note 3
×
3 3
Note 3 Note 3
× ×
1 1 0
× ×
1 1 0
n+1 n+1
Note 4 Note 4
n+2 n+2
Note 4 Note 4
Note 17 Note 17
(3/5)
SAT