Table of Contents
Advertisement
11.8.7 Baud rate control function
(1) Prescaler
The V850E/IA1 includes a prescaler for dividing the CAN module clock (f
clock (f
) that is based on a division ratio ranging from 2 to 128 applied to the CAN module clock when the
BTL
C1BRP register's TLM bit = 0 and based on a division ratio ranging from 2 to 256 applied to the CAN module
clock when the TLM bit = 1 (refer to 11.10 (26) CAN1 bit rate prescaler register (C1BRP)).
(2) Nominal bit time (8 to 25 time quantum)
A definition of 1 data bit time is shown below.
Remark
1 time quantum = 1/f
Sync segment
Segment Name
Sync segment
(Synchronization Segment)
Prop segment
(Propagation Segment)
Phase segment 1
(Phase Buffer Segment 1)
Phase segment 2
(Phase Buffer Segment 2)
SJW
(reSynchronization Jump Width)
Note IPT: Information Processing Time
544
CHAPTER 11 FCAN CONTROLLER
BTL
Figure 11-20. Nominal Bit Time
Nominal bit time
Prop segment
Phase segment 1
SJW
Segment Length
1
This segment begins when resynchronization occurs.
1 to 8 (programmable)
This segment is used to absorb the delays caused by
the output buffer, CAN bus, and input buffer.
It is set to return an ACK signal until phase segment 1
begins.
Prop segment time ≥ (output buffer delay) + (CAN bus
delay) + (input buffer delay)
1 to 8 (programmable)
This segment is used to compensate for errors in the
data bit time. It accommodates a wide margin or error
but slows down communication speed.
Maximum value from
Note
phase segment 1, IPT
(IPT = 0 to 2)
1 to 4 (programmable)
This sets the range for bit synchronization.
User's Manual U14492EJ3V0UD
). This prescaler generates a
MEM
Phase segment 2
SJW
Sample point
Description
Advertisement
Table of Contents
