NEC V850E/IA1 mPD703116 User Manual page 176

32-bit single-chip microcontrollers
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Figure 7-6. Example of Servicing in Which Another Interrupt Request Is Issued While an
Interrupt Is Being Serviced (1/2)
Main routine
EI
Interrupt request a
(level 3)
Interrupt request c
Interrupt request d
(level 3)
Interrupt request e
Interrupt request f
(level 2)
Interrupt request g
(level 1)
Caution The values of the EIPC and EIPSW registers must be saved before executing multiple
interrupts. When returning from multiple interrupt servicing, restore the values of EIPC and
EIPSW after executing the DI instruction.
Remarks 1. a to u in the figure are the temporary names of interrupt requests shown for the sake of
explanation.
2. The default priority in the figure indicates the relative priority between two interrupt requests.
176
CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION
Servicing of a
EI
Interrupt
request b
(level 2)
Servicing of c
(level 2)
Servicing of d
Servicing of e
EI
(level 3)
Servicing of f
Servicing of g
EI
Interrupt request h
(level 1)
Servicing of h
User's Manual U14492EJ3V0UD
Servicing of b
Interrupt request b is acknowledged because the
priority of b is higher than that of a and interrupts are
enabled.
Although the priority of interrupt request d is higher
than that of c, d is held pending because interrupts
are disabled.
Interrupt request f is held pending even if interrupts are
enabled because its priority is lower than that of e.
Interrupt request h is held pending even if interrupts are
enabled because its priority is the same as that of g.

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