NEC V850E/IA1 mPD703116 User Manual page 155

32-bit single-chip microcontrollers

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Figure 6-4 shows a single transfer mode example in which a lower priority DMA transfer request is generated

within one clock after the end of a single transfer. DMA channels 0 and 3 are used for a single transfer. When two

DMA transfer request signals are activated at the same time, the two DMA transfers are performed alternately.

(Internal signal)

(Internal signal)

Note The bus is always released.

Figure 6-5 shows a single transfer mode example in which two or more lower priority DMA transfer requests are

generated within one clock after the end of a single transfer. DMA channels 0, 2, and 3 are used for a single transfer.

When three or more DMA transfer request signals are activated at the same time, always the two highest priority DMA

transfers are performed alternately.

(Internal signal)

(Internal signal)

(Internal signal)

CPU DMA3 CPU

Note The bus is always released.

CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER)

Figure 6-4. Single Transfer Example 3

DMA0 CPU DMA0

Figure 6-5. Single Transfer Example 4

User's Manual U14492EJ3V0UD

DMA channel 3

terminal count

DMA3 CPU DMA2 CPU

DMA channel 0

terminal count

DMA0 CPU DMA0

DMA channel 0

terminal count

DMA channel 3

terminal count

DMA channel 2

terminal count