NEC V850E/IA1 mPD703116 User Manual page 546

32-bit single-chip microcontrollers
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(b) Resynchronization
Resynchronization is performed when a level change is detected on the bus during a receive operation.
• The edge's phase error is produced by the relative positions of the detected edge and sync segment.
<Phase error symbols>
0:
Positive: Edge is before sample point (phase error)
Negative: Edge is after sample point (phase error)
• When the edge is detected as within the bit timing specified by the SJW, synchronization is performed
in the same way as hardware synchronization.
• When the edge is detected as extending beyond the bit timing specified by the SJW, synchronization
is performed on the following basis.
When phase error is positive: Phase segment 1 is lengthened to equal the SJW
When phase error is negative: Phase segment 2 is shortened to equal the SJW
• A "shifting" of the baud rate for the transmitting and receiving nodes moves the relative position of the
sample point for data on the receiving node.
CAN bus
Bit timing
546
CHAPTER 11 FCAN CONTROLLER
When edge is within sync segment
Figure 11-22. Resynchronization
Previous bit
SOF
Sync
Prop
segment
segment
SJW
User's Manual U14492EJ3V0UD
Next bit
Phase
Phase
segment 1
segment 2

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