NEC V850E/IA1 mPD703116 User Manual page 137

Figure 5-1. SRAM, External ROM, External I/O Access Timing (5/5)
CLKOUT (Output)
HLDRQ (Input)
HLDAK (Output)
A16 to A23 (Output)
Note 2
AD0 to AD15 (I/O)
ASTB (Output)
RD (Output)
UWR, LWR (Output)
CSn (Output)
WAIT (Input)
Notes 1. On a read: Undefined
On a write: Address
2. On a read: Data
On a write: Undefined
Remarks 1. The circles indicate the sampling timing.
2. Broken lines indicate high impedance.
3. n = 0 to 7
CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION
(e) Bus hold timing
T2 T3
Note 1
Undefined
User's Manual U14492EJ3V0UD
TH TH TH TH TI T1
Undefined Address
Undefined Address
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