Table of Contents
Advertisement
CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT)
Figure 9-46. TM1n Block Diagram (During PWM Output Operation)
f
/2
CLK
f
/4
CLK
f
/8
CLK
f
/16
CLK
f
/32
CLK
f
/64
CLK
f
/128
CLK
Caution Be sure to set the count clock of TM1n to 8 MHz or lower.
Remarks 1. f
: Base clock
CLK
2. n = 0, 1
(i) Description of operation
The CM1n0 register is a compare register used to set the PWM output cycle. When the value of this
register matches the value of TM1n, the INTCM1n0 interrupt is generated. Compare match is saved
by hardware, and TM1n is cleared at the next count clock after the match.
The CM1n1 register is a compare register used to set the PWM output duty. Set the duty required for
the PWM cycle.
Figure 9-47. PWM Signal Output Example (When ALVT10 Bit = 0 Is Set)
INTCM1n0
INTCM1n1
Cautions 1. Changing the values of the CM1n0 and CM1n1 registers is prohibited during TM1n operation
(TM1CEn bit of TMC1n register = 1).
2. Changing the value of the ALVT10 bit of the TUMn register is prohibited during TM1n
operation.
3. PWM signal output is performed from the second PWM cycle after the TM1CEn bit is set (to
"1").
Clear
TM1n (16 bits)
16
Compare register
S
(CM1n0)
16
R
Compare register
(CM1n1)
CM1n0 set value
TM1n
CM1n1 set value
TO1n
User's Manual U14492EJ3V0UD
INTCM1n0
ALVT10
TUMn register
Q
INTCM1n1
TO1n
321
Advertisement
Table of Contents
