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Setting data to the flash programming mode control register (FLPMC) is performed in the following sequence.
<1> Disable interrupts (set the NP bit and ID bit of the PSW to 1).
<2> Prepare the data to be set in the specific register in a general-purpose register.
<3> Write data to the peripheral command register (PHCMD).
<4> Set the flash programming mode control register (FLPMC) by executing the following instructions.
• Store instruction (ST/SST instructions)
• Bit manipulation instruction (SET1/CLR1/NOT1 instructions)
<5> Insert NOP instructions (5 instructions (<5> to <9>)).
<10> Cancel the interrupt disabled state (reset the NP bit of the PSW to 0).
[Description example]
Remark rX: Value written to the PSW
rY: Value returned to the PSW
No special sequence is required for reading a specific register.
Cautions 1. If an interrupt is acknowledged between when PHCMD is issued (<3>) and writing to a
specific register (<4>) immediately after issuing PHCMD, writing to the specific register may
not be performed and a protection error may occur (the PRERR bit of the PHS register = 1).
Therefore, set the NP bit of the PSW to 1 (<1>) to disable interrupt acknowledgement.
Similarly, disable acknowledgement of interrupts when a bit manipulation instruction is
used to set a specific register.
2. Use the same general-purpose register used to set a specific register (<3>) for writing to the
PHCMD register (<4>) even though the data written to the PHCMD register is dummy data.
This is the same as when a general-purpose register is used for addressing.
3. Before executing this processing, complete all DMA transfer operations.
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CHAPTER 16 FLASH MEMORY ( µ µ µ µ PD70F3116)
<1> LDSR
rX, 5
<2> MOV
0x02, r10
<3> ST.B
r10, PHCMD[r0]
<4> ST.B
r10, FLPMC[r0]
<5> NOP
<6> NOP
<7> NOP
<8> NOP
<9> NOP
<10> LDSR
rY, 5
User's Manual U14492EJ3V0UD
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