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Figure No.
11-11 Arbitration Field (In Extended Format Mode)................................................................................................533
11-12 Control Field .................................................................................................................................................534
11-13 Data Field .....................................................................................................................................................535
11-14 CRC Field .....................................................................................................................................................535
11-15 ACK Field .....................................................................................................................................................536
11-16 End of Frame (EOF) .....................................................................................................................................536
11-17 Interframe Space ..........................................................................................................................................537
11-18 Error Frame ..................................................................................................................................................538
11-19 Overload Frame............................................................................................................................................539
11-20 Nominal Bit Time ..........................................................................................................................................544
11-21 Coordination of Data Bit Synchronization .....................................................................................................545
11-22 Resynchronization ........................................................................................................................................546
11-23 Example of Bit Setting/Clearing Operations .................................................................................................547
11-24 16-Bit Data During Write Operation ..............................................................................................................548
11-25 FCAN Clocks ................................................................................................................................................575
11-26 Initialization Processing ................................................................................................................................601
11-27 CAN Main Clock Selection Register (CGCS) Settings..................................................................................602
11-28 CAN Global Interrupt Enable Register (CGIE) Settings................................................................................602
11-29 CAN Global Status Register (CGST) Settings ..............................................................................................603
11-30 CAN1 Bit Rate Prescaler Register (C1BRP) Settings...................................................................................603
11-31 CAN1 Synchronization Control Register (C1SYNC) Settings .......................................................................604
11-32 CAN1 Interrupt Enable Register (C1IE) Settings ..........................................................................................605
11-33 CAN1 Definition Register (C1DEF) Settings.................................................................................................606
11-34 CAN1 Control Register (C1CTRL) Settings ..................................................................................................607
11-35 CAN1 Address Mask a Registers L and H (C1MASKLa and C1MASKHa) (a = 0 to 3) Settings ..................608
11-36 Message Buffer Settings ..............................................................................................................................609
11-37 CAN Message Configuration Registers 00 to 31 (M_CONF00 to M_CONF31) Settings..............................610
11-38 CAN Message Control Registers 00 to 31 (M_CTRL00 to M_CTRL31) Settings .........................................611
11-39 Transmit Setting ...........................................................................................................................................612
11-40 Receive Setting ............................................................................................................................................613
11-41 CAN Sleep Mode Settings ............................................................................................................................614
11-42 Clearing of CAN Sleep Mode by CAN Bus Active Status .............................................................................614
11-43 Clearing of CAN Sleep Mode by CPU ..........................................................................................................615
11-44 CAN Stop Mode Settings..............................................................................................................................615
11-45 Clearing of CAN Stop Mode .........................................................................................................................616
11-46 C1SYNC Register Settings...........................................................................................................................620
11-47 Sequential Data Read ..................................................................................................................................622
12-1
Image of NBD Space....................................................................................................................................628
12-2
Basic Protocol...............................................................................................................................................629
13-1
Block Diagram of A/D Converter 0 or 1 ........................................................................................................647
13-2
Block Diagram of Trigger Source Switching Circuit in Timer Trigger Mode ..................................................648
13-3
Relationship Between Analog Input Voltages and A/D Conversion Results .................................................657
24
LIST OF FIGURES (6/8)
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User's Manual U14492EJ3V0UD
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