NEC V850E/IA1 mPD703116 User Manual page 248

CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT)
(6) PWM software timing output registers 0, 1 (PSTO0, PSTO1)
The PSTOn register is used to perform settings to output the desired waveforms to the external pulse output
pins (TO0n0 to TO0n5) by software.
PSTOn can be read/written in 8-bit or 1-bit units.
Cautions 1. When the value of the TORTOn bit has been changed from 0 to 1 during timer output
(setting changed to software output), the timing is delayed by the dead-time portion
when the output level differs from the timer output signal during output due to the
settings of the UPORTn, VPORTn, and WPORTn bits.
When the output level is the same as the timer output signal during output due to the
settings of the UPORTn, VPORTn, and WPORTn bits, output is performed maintaining
the same output level.
2. If software output is enabled (TORTOn bit = 1), the INTTM0n and INTCM0n3 interrupts
and TO0n0 to TO0n5 output statuses are as follows during TM0n operation (TM0CEn bit
= 1).
INTTM0n and INTCM0n3 interrupts: Continue occurring at each timing in accordance
TO0n0 to TO0n5 outputs:
3. If the TORTOn bit is changed from 1 to 0 during TM0n operation (TM0CEn bit = 1), the
software output state is retained for the TO0n0 to TO0n5 outputs until one of the
set/reset condition of the flip-flop for the TO0n0 to TO0n5 outputs shown in (a) below is
generated.
(a) Set/reset conditions of flip-flop for TO0n0 to TO0n5 outputs
Set
Reset
Remark n = 0, 1
4. If the same value is written to the UPORTn (VPORTn, WPORTn) bit when TORTOn = 1,
the TO0n0 and TO0n1 outputs (TO0n2 and TO0n3, TO0n4 and TO0n5) are not changed.
248
Output Status Operation Mode
Timer output Triangular wave mode
(PWM mode 0, 1)
Sawtooth wave mode
(PWM mode 2)
Software output
Timer output Triangular wave mode
(PWM mode 0, 1)
Sawtooth wave mode
(PWM mode 2)
Software output
User's Manual U14492EJ3V0UD
with timer and compare operations.
Software output has priority.
Compare match while TM0n is counting up
Match between TM0n and CM0n3 registers
−
Set (to 1) UPORTn, VPORTn, and WPORTn bits
Compare match while TM0n is counting down
Compare match with TM0n
−
Clear (to 0) UPORTn, VPORTn, and WPORTn bits
Conditions