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4.3
Memory Block Function ..........................................................................................................111
4.3.1
Chip select control function ........................................................................................................112
4.4
Bus Cycle Type Control Function ..........................................................................................115
4.5
Bus Access...............................................................................................................................116
4.5.1
Number of access clocks ...........................................................................................................116
4.5.2
Bus sizing function .....................................................................................................................117
4.5.3
Word data processing format .....................................................................................................117
4.5.4
Bus width....................................................................................................................................118
4.6
Wait Function ...........................................................................................................................124
4.6.1
Programmable wait function.......................................................................................................124
4.6.2
External wait function .................................................................................................................126
4.6.3
Relationship between programmable wait and external wait......................................................126
4.7
Idle State Insertion Function...................................................................................................127
4.8
Bus Hold Function ...................................................................................................................128
4.8.1
Function outline ..........................................................................................................................128
4.8.2
Bus hold procedure ....................................................................................................................128
4.8.3
Operation in power save mode ..................................................................................................129
4.8.4
Bus hold timing...........................................................................................................................129
4.9
Bus Priority Order ....................................................................................................................130
4.10 Boundary Operation Conditions ............................................................................................131
4.10.1
Program space...........................................................................................................................131
4.10.2
Data space .................................................................................................................................131
CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION .................................................................132
5.1
SRAM, External ROM, External I/O Interface.........................................................................132
5.1.1
Features .....................................................................................................................................132
5.1.2
SRAM, external ROM, external I/O access ................................................................................133
CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) ....................................................................138
6.1
Features ....................................................................................................................................138
6.2
Configuration............................................................................................................................139
6.3
Control Registers .....................................................................................................................140
6.3.1
DMA source address registers 0 to 3 (DSA0 to DSA3) ..............................................................140
6.3.2
DMA destination address registers 0 to 3 (DDA0 to DDA3) .......................................................142
6.3.3
DMA transfer count registers 0 to 3 (DBC0 to DBC3) ................................................................144
6.3.4
DMA addressing control registers 0 to 3 (DADC0 to DADC3)....................................................145
6.3.5
DMA channel control registers 0 to 3 (DCHC0 to DCHC3) ........................................................147
6.3.6
DMA disable status register (DDIS)............................................................................................149
6.3.7
DMA restart register (DRST) ......................................................................................................149
6.3.8
DMA trigger factor registers 0 to 3 (DTFR0 to DTFR3) ..............................................................150
6.4
DMA Bus States .......................................................................................................................152
6.4.1
Types of bus states ....................................................................................................................152
6.4.2
DMAC bus cycle state transition ................................................................................................153
6.5
Transfer Mode ..........................................................................................................................154
6.5.1
Single transfer mode ..................................................................................................................154
6.5.2
Single-step transfer mode ..........................................................................................................156
6.5.3
Block transfer mode ...................................................................................................................156
6.6
Transfer Types .........................................................................................................................157
User's Manual U14492EJ3V0UD
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