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ADn_DBG
1st
2nd
Caution Read data is 8-bit fixed-length.
12.4.2 Event detection function
By having a comparator (24-bit address setting) for match detection on-chip at a single point, this function detects
match of the address setting registers shown below and outputs a match trigger (falling edge) to the NBD tool. Event
trigger output is low active and during the active period it is output synchronous with the system clock of the target
CPU. The active width is one cycle of the internal system clock of the CPU.
(1) Event detection conditions
• Execution PC address match
Match detection range for timing of a write to a set address in the internal RAM area
XFFFC000H to XFFFE7FFH
(2) Event detection function control register
(a) NBD event condition setting register (EVTU_C)
7
EVTU_C7 to
0
EVTU_C0
Bit Position
Bit Name
0
PCU/DTU
634
CHAPTER 12 NBD FUNCTION ( µ µ µ µ PD70F3116)
Table 12-8. Data Packet
AD3_DBG
AD2_DBG
D3
D7
6
5
4
0
0
0
Selects an execution PC event or RAM access event.
0: Internal RAM access event is in valid
1: Execution PC event is in valid
Note
If the EVTU_C register is set outside the internal RAM area, an event also
is output when writing outside the RAM.
User's Manual U14492EJ3V0UD
AD1_DBG
D2
D1
D6
D5
3
2
1
0
0
0
PCU/DTU
Function
Note
AD0_DBG
D0
D4
0
NBD space address
Initial value
820H
Undefined
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