Table of Contents
Advertisement
12.7 Initialization Required for DMA (2 Channels)
(1) The DMA initialization in a setting change request must be performed by user software.
(2) Assign DMA two channels in NBD.
At this time, assign an NBDAD interrupt to a higher priority channel than an NBDREW interrupt.
(3) Initialize registers of the channel to which the NBDAD interrupt is assigned.
Set contents so that the contents of NBDMSL/NDBMSH and NBDMDL/NBDMDH (read-only SFR) transfer to
DMA source address registers nL and nH (DSAnL, DSAnH)
nH (DDAnL, DDAnH)
3).
Note DMA registers are 16-bit access only.
(4) Set DMA addressing control register n (DADCn) of the DMA channel assigned to the NBDREW interrupt for
32-bit transfer (bit transfer settings of 8 bits × 4, 16 bits × 2, and 32 bits × 1
the counter direction of the DMA transfer source address and DMA transfer destination address to increment
mode (SADm bit of DADCn register = 0, DADm bit = 0 (m = 0,1)) (since DMA judges data transfer terminated
on reading or writing the uppermost 8 bits).
Note Bits that can be manipulated on 8 bits × 4, 16 bits × 2, and 32 bits × 1 bit transfer are shown below.
8 bits × 4: 32-, 16-, or 8-bit read is possible.
16 bits × 2: 16- or 8-bit read is possible.
32 bits × 1: 32-bit read is possible. This is the highest read speed.
Settings other than the above are prohibited. Moreover, make the setting 32 bits × 1 when reading
or writing RAM.
Caution In DMA initialization, set the DMA request selection last.
CHAPTER 12 NBD FUNCTION ( µ µ µ µ PD70F3116)
of the DMA channel assigned to the NBDREW interrupt in 16 bits × 4 blocks (n = 0 to
Note
User's Manual U14492EJ3V0UD
Note
and DMA destination address registers nL and
Note
) (n = 0 to 3). In addition, set
641
Advertisement
Table of Contents
