NEC V850E/IA1 mPD703116 User Manual page 320

CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT)
(d) Capture function
TM1n connects two capture/compare register (CC1n0, CC1n1) channels.
When CC1n0 and CC1n1 are set to the capture register mode, the value of TM1n is captured in
synchronization with the corresponding capture trigger signal.
Furthermore, an interrupt request (INTCC1n0, INTCC1n1) is generated by the INTP1n0, INTP1n1 input
signals.
Table 9-6. Capture Trigger Signal (TM1n) to 16-Bit Capture Register
Remarks 1. CC1n0 and CC1n1 are capture/compare registers. Which of these registers is used is
The valid edge of the capture trigger is specified by signal edge selection register 1n (SESA1n). If both
the rising edge and the falling edge are selected as the capture triggers, it is possible to measure the
input pulse width from external. If a single edge is selected as the capture trigger, the input pulse cycle
can be measured.
(e) PWM output operation
PWM output operation is performed from the TO1n pin by setting TM1n to the general-purpose timer
mode (CMD bit = 0) using timer unit mode register n (TUMn).
The resolution is 16 bits, and the count clock can be selected from among seven internal clocks (f
f /4, f /8, f
CLK CLK
320
Capture Register
CC1n0
CC1n1
specified with capture/compare control register n (CCRn).
2. n = 0, 1
/16, f /32, f /64, f
CLK CLK CLK CLK
User's Manual U14492EJ3V0UD
Capture Trigger Signal
INTP1n0
INTP1n0 or INTP1n1
/128).
/2,
CLK