NEC V850E/IA1 mPD703116 User Manual page 506

CHAPTER 10 SERIAL INTERFACE FUNCTION
Figure 10-28. Timing Chart of Interrupt Request Signal Output in Delay Mode (2/2)
(b) When CKP bit = 1, DAP bit = 1
Input clock
SCKn (I/O)
SIn (input) DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0
SOn (output) DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0
Reg_R/W
INTCSIn
interrupt
CSOTn bit
Delay
Remarks 1. n = 0, 1
2. Reg_R/W: Internal signal. This signal indicates that receive data buffer register (SIRBn/
SIRBLn) read or transmit data buffer register (SOTBn/SOTBLn) write was
performed.
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User's Manual U14492EJ3V0UD