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CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT)
(2) Dead-time timers 00 to 02, 10 to 12 (DTM00 to DTM02, DTM10 to DTM12)
DTMn0 to DTMn2 are dedicated 12-bit down timers that generate dead time suitable for inverter control
application. DTMn0 to DTMn2 operate as one-shot timers.
Counting by a dead-time timer is enabled or disabled by the TM0CEDn bit of timer control register 0n
(TMC0n) and cannot be controlled by software. Dead-time timer count start and stop is controlled by
hardware.
A dead-time timer starts counting down when the value of the dead-time timer reload register n (DTRRn) is
transferred in synchronization with the compare match timing of CM0n0 to CM0n2.
When the value of a dead-time timer changes from 000H to FFFH, the dead-time timer generates an
underflow signal, and the timer stops at the value FFFH.
If the value of a dead-time timer matches the value of the corresponding compare register before underflow of
the dead-time timer takes place, the value of DTRRn is transferred to the dead-time timer again, and the
timer starts down counting.
The count clock of the dead-time timer is fixed to the base clock (f
of DTRRn + 1)/base clock (f
If TM0n operates in PWM mode 0, PWM mode 1 with the dead-time timer count operation disabled, an
inverted signal without dead time is output to TO0n0 and TO0n1, TO0n2 and TO0n3, and TO0n4 and TO0n5.
(3) Dead-time timer reload registers 0, 1 (DTRR0, DTRR1)
DTRRn register is a 12-bit register used to set the values of the three dead-time timers (DTMn0 to DTMn2
registers) (n = 0, 1). However, a value is transferred from the DTRRn register to each dead-time register
independently.
DTRRn can be read/written in 16-bit units. All 0s are read for the higher 4 bits when 16-bit read access is
performed to the DTRRn register.
15
14
13
DTRR0
0
0
0
15
14
13
DTRR1
0
0
0
Cautions 1. Changing the value of the DTRRn register during TM0n operation (TM0CEn bit of TMC0n
register = 1) is prohibited.
2. Be sure to write 0 to the higher 4 bits.
(4) Compare registers 000 to 002, 010 to 012 (CM000 to CM002, CM010 to CM012)
CM0n0 to CM0n2 are 16-bit registers that always compare their own values with the value of TM0n. If the
value of a compare register matches the value of TM0n, the compare register outputs a trigger signal, and
changes the contents of the flip-flop (F/F) connected to the compare register. Each of CM0n0 to CM0n2 is
provided with a buffer register (BFCMn0 to BFCMn2), so that the contents of the buffer are transferred to
CM0n0 to CM0n2 at the following base clock (f
TMC0n register.
).
CLK
12
11
10
9
8
7
0
12
11
10
9
8
7
0
CLK
User's Manual U14492EJ3V0UD
), and the dead-time width is (set value
CLK
6
5
4
3
2
1
6
5
4
3
2
1
). Transfer is enabled or disabled by the BFTEN bit of the
0
Address
Initial value
FFFFF570H
0FFFH
0
Address
Initial value
FFFFF5B0H
0FFFH
231
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