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16.8 How to Distinguish Flash Memory and Mask ROM Versions
It is possible to distinguish a flash memory version ( µ PD70F3116) and a mask ROM version ( µ PD703116) by
means of software, using the methods shown below.
<1> Disable interrupts (set the NP bit of PSW to 1).
<2> Write data to the peripheral command register (PHCMD).
<3> Set the VPPDIS bit of the flash programming mode control register (FLPMC) to 1.
<4> Insert NOP instructions (5 instructions (<4> to <8>)).
<9> Cancel the interrupt disabled state (reset the NP bit of the PSW to 0).
<10> Read the VPPDIS bit of the flash programming mode control register (FLPMC).
• If the value read is 0: Mask ROM version ( µ PD703116)
• If the value read is 1: Flash memory version ( µ PD70F3116)
[Description example]
Remark rX: Value written to the PSW
rY: Value returned to the PSW
Cautions 1. If an interrupt is acknowledged between when PHCMD is issued (<2>) and writing to a
specific register (<3>) immediately after issuing PHCMD, writing to a specific register may
not be performed and a protection error may occur (the PRERR bit of the PHS register = 1).
Therefore, set the NP bit of the PSW to 1 (<1>) to disable interrupt acknowledgement.
Similarly, disable acknowledgement of interrupts when a bit manipulation instruction is
used to set a specific register.
2. When a store instruction is used for setting a specific register, be sure to use the same
general-purpose register used to set the specific register for writing to the PHCMD register
even though the data written to the PHCMD register is dummy data. This is the same as
when a general-purpose register is used for addressing.
3. Before executing this processing, complete all DMA transfer operations.
760
CHAPTER 16 FLASH MEMORY ( µ µ µ µ PD70F3116)
<1> LDSR
rX, 5
<2> ST.B
r10, PHCMD[r0]
<3> SET1
3, FLPMC[r0]
<4> NOP
<5> NOP
<6> NOP
<7> NOP
<8> NOP
<9> LDSR
rY, 5
<10> TST1
3, FLPMC[r0]
BNZ
BR
User's Manual U14492EJ3V0UD
<Start address of self-programming routine>
<Routine when writing is not performed>
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