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12.6 Restrictions on NBD
12.6.1 General restrictions
(1) CLK_DBG operates at less than half the speed of the internal system clock (f
(2) If a command packet is sent during a reset period, "ready" is not returned afterwards. Reset again.
12.6.2 Restrictions related to read or write of RAM by NBD
(1) Initialize DMA in user software.
(2) Writes to RAM are 32-bit fixed-length only.
On a read-only, RAM can be accessed in 32-, 16-, or 8-bit units.
On a read/write, RAM can be accessed in 32-bit units.
(3) NBD does not function from during a reset until DMA initialization after the reset finishes.
If a read or write of RAM is performed in this interval, NBD does not return "ready" afterwards. Reset again.
12.6.3 Restrictions related to NBD event trigger function
(1) If a ROM execution address event trigger is set to the address after a branch instruction, an event is
generated due to pipeline processing even if it is not executed. The trigger must be set to an address at least
32 bits × 3 words after a branch instruction.
(2) Since an event trigger is cleared by a reset, it must be set again after a reset.
(3) Unless there is a ROM fetch, a trigger occurs even on a read.
(4) ROM address match functions only for internal ROM. The lower 2 bits are masked.
RAM address match functions only for internal RAM. The lower 2 bits are masked.
Caution ROM and RAM address match cannot be used in the in-circuit emulator.
12.6.4 How to detect termination of DMA initialization via NBD tool
Set an event trigger using a RAM write and send a write command from NBD to the relevant address. If an event
trigger occurs at this time, DMA initialization has terminated.
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CHAPTER 12 NBD FUNCTION ( µ µ µ µ PD70F3116)
User's Manual U14492EJ3V0UD
) and is 12.5 MHz maximum.
XX
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