Stack Pointer; Instruction Execution Timing - Atmel AT90PWM2 Manual

5.6

Stack Pointer

5.7

Instruction Execution Timing

4317I–AVR–01/08
X-register 7
R27 (0x1B)
15
Y-register 7
R29 (0x1D)
15
Z-register 7
R31 (0x1F)
In the different addressing modes these address registers have functions as fixed displacement,
automatic increment, and automatic decrement (see the instruction set reference for details).
The Stack is mainly used for storing temporary data, for storing local variables and for storing
return addresses after interrupts and subroutine calls. The Stack Pointer Register always points
to the top of the Stack. Note that the Stack is implemented as growing from higher memory loca-
tions to lower memory locations. This implies that a Stack PUSH command decreases the Stack
Pointer.
The Stack Pointer points to the data SRAM Stack area where the Subroutine and Interrupt
Stacks are located. This Stack space in the data SRAM must be defined by the program before
any subroutine calls are executed or interrupts are enabled. The Stack Pointer must be set to
point above 0x100. The Stack Pointer is decremented by one when data is pushed onto the
Stack with the PUSH instruction, and it is decremented by two when the return address is
pushed onto the Stack with subroutine call or interrupt. The Stack Pointer is incremented by one
when data is popped from the Stack with the POP instruction, and it is incremented by two when
data is popped from the Stack with return from subroutine RET or return from interrupt RETI.
The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of
bits actually used is implementation dependent. Note that the data space in some implementa-
tions of the AVR architecture is so small that only SPL is needed. In this case, the SPH Register
will not be present.
Bit 15 14
SP15 SP14
SP7 SP6
7 6
Read/Write R/W R/W
R/W R/W
Initial Value 0 0
0 0
This section describes the general access timing concepts for instruction execution. The AVR
CPU is driven by the CPU clock clk
chip. No internal clock division is used.
Figure 5-4 shows the parallel instruction fetches and instruction executions enabled by the Har-
vard architecture and the fast-access Register File concept. This is the basic pipelining concept
to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost,
functions per clocks, and functions per power-unit.
0 7
R26 (0x1A)
YH
0 7
R28 (0x1C)
ZH
0 7
R30 (0x1E)
13 12 11
SP13 SP12 SP11
SP5 SP4 SP3
5 4 3
R/W R/W R/W
R/W R/W R/W
0 0 0
0 0 0
, directly generated from the selected clock source for the
CPU
AT90PWM2/3/2B/3B
YL
ZL
0
10 9 8
SP10 SP9 SP8
SP2 SP1 SP0
2 1 0
R/W R/W R/W
R/W R/W R/W
0 0 0
0 0 0
0
0
0
0
SPH
SPL
15