Atmel AT90PWM2 Manual page 75

AT90PWM2/3/2B/3B
76
XCK, USART External clock. The Data Direction Register (DDD0) controls whether the clock is
output (DDD0 set) or input (DDD0 cleared). The XCK0 pin is active only when the USART oper-
ates in Synchronous mode.
SS_A: Slave Port Select input. When the SPI is enabled as a slave, this pin is configured as an
input regardless of the setting of DDD0. As a slave, the SPI is activated when this pin is driven
low. When the SPI is enabled as a master, the data direction of this pin is controlled by DDD0.
When the pin is forced to be an input, the pull-up can still be controlled by the PORTD0 bit.
Table 11-10 and Table 11-11
shown in Figure 11-5 on page
Table 11-10. Overriding Signals for Alternate Functions PD7..PD4
PD7/
Signal Name ACMP0
PUOE 0
PUOV 0
DDOE 0
DDOV 0
PVOE 0
PVOV 0
DIEOE ACMP0D
DIEOV 0
DI –
AIO ACOMP0
relates the alternate functions of Port D to the overriding signals
67.
PD6/ADC3/
ACMPM/INT0
0
0
0
0
0
0
ADC3D + In0en
In0en
INT0
ADC3
ACMPM
PD5/ADC2/ PD4/ADC1/RXD/
ACMP2 ICP1A/SCK_A
RXEN + SPE •
0
MSTR • SPIPS
PD4 •
0
PUD
RXEN + SPE •
0
MSTR • SPIPS
0 0
SPE • MSTR •
0
SPIPS
0 –
ADC2D ADC1D
0 0
ICP1A
ADC2
ADC1
ACOMP2
4317I–AVR–01/08