Atmel AT90PWM2 Manual page 242

21.6.3 Offset Compensation Schemes
21.6.4 ADC Accuracy Definitions
4317I–AVR–01/08
The gain stage has a built-in offset cancellation circuitry that nulls the offset of differential mea-
surements as much as possible. The remaining offset in the analog path can be measured
directly by shortening both differential inputs using the AMPxIS bit with both inputs unconnected.
(See "Amplifier 0 Control and Status register – AMP0CSR" on page 256.
1Control and Status register – AMP1CSR" on page
tracted in software from the measurement results. Using this kind of software based offset
correction, offset on any channel can be reduced below one LSB.
An n-bit single-ended ADC converts a voltage linearly between GND and V
(LSBs). The lowest code is read as 0, and the highest code is read as 2
Several parameters describe the deviation from the ideal behavior:
• Offset: The deviation of the first transition (0x000 to 0x001) compared to the ideal transition
(at 0.5 LSB). Ideal value: 0 LSB.
Figure 21-10. Offset Error
Output Code
• Gain Error: After adjusting for offset, the Gain Error is found as the deviation of the last
transition (0x3FE to 0x3FF) compared to the ideal transition (at 1.5 LSB below maximum).
Ideal value: 0 LSB
257.). This offset residue can be then sub-
Offset
Error
AT90PWM2/3/2B/3B
and See "Amplifier
REF
n
-1.
Ideal ADC
Actual ADC
V
Input Voltage
REF
n
in 2 steps
243