Watchdog Timer - Atmel AT90PWM2 Manual

8-bit avr microcontroller with 8k bytes in-system programmable flash
Table of Contents

Advertisement

AT90PWM2/3/2B/3B
52
– Interrupt and System Reset
Selectable Time-out period from 16ms to 8s
Possible Hardware fuse Watchdog always on (WDTON) for fail-safe mode
Figure 9-7.

Watchdog Timer

128 KHz
OSCILLATOR
WDP3
WDIF
WDIE
The Watchdog Timer (WDT) is a timer counting cycles of a separate on-chip 128 kHz oscillator.
The WDT gives an interrupt or a system reset when the counter reaches a given time-out value.
In normal operation mode, it is required that the system uses the WDR - Watchdog Timer Reset
- instruction to restart the counter before the time-out value is reached. If the system doesn't
restart the counter, an interrupt or system reset will be issued.
In Interrupt mode, the WDT gives an interrupt when the timer expires. This interrupt can be used
to wake the device from sleep-modes, and also as a general system timer. One example is to
limit the maximum time allowed for certain operations, giving an interrupt when the operation
has run longer than expected. In System Reset mode, the WDT gives a reset when the timer
expires. This is typically used to prevent system hang-up in case of runaway code. The third
mode, Interrupt and System Reset mode, combines the other two modes by first giving an inter-
rupt and then switch to System Reset mode. This mode will for instance allow a safe shutdown
by saving critical parameters before a system reset.
The "Watchdog Timer Always On" (WDTON) fuse, if programmed, will force the Watchdog Timer
to System Reset mode. With the fuse programmed the System Reset mode bit (WDE) and Inter-
rupt mode bit (WDIE) are locked to 1 and 0 respectively. To further ensure program security,
alterations to the Watchdog set-up must follow timed sequences. The sequence for clearing
WDE and changing time-out configuration is as follows:
1. In the same operation, write a logic one to the Watchdog change enable bit (WDCE) and
WDE. A logic one must be written to WDE regardless of the previous value of the WDE
bit.
2. Within the next four clock cycles, write the WDE and Watchdog prescaler bits (WDP) as
desired, but with the WDCE bit cleared. This must be done in one operation.
MCU RESET
INTERRUPT
4317I–AVR–01/08

Advertisement

Table of Contents
loading
Need help?

Need help?

Do you have a question about the AT90PWM2 and is the answer not in the manual?

Subscribe to Our Youtube Channel

This manual is also suitable for:

At90pwm3At90pwm2bAt90pwm3b

Table of Contents