Atmel AT90PWM2 Manual page 303

26.6 SPI Timing Characteristics
AT90PWM2/3/2B/3B
304
See Figure 26-3 and Figure 26-4
Table 26-4. SPI Timing Parameters
Description
1 SCK period
2 SCK high/low
3 Rise/Fall time
4 Setup
5 Hold
6 Out to SCK
7 SCK to out
8 SCK to out high
9 SS low to out
10 SCK period
11 SCK high/low
12 Rise/Fall time
13 Setup
14 Hold
15 SCK to out
16 SCK to SS high
17 SS high to tri-state
18 SS low to SCK
Note: In SPI Programming mode the minimum SCK high/low period is:
- 2 t for f < 12 MHz
CLCL CK
- 3 t for f >12 MHz
CLCL CK
Figure 26-3. SPI Interface Timing Requirements (Master Mode)
SS
SCK
(CPOL = 0)
SCK
(CPOL = 1)
MISO
(Data Input)
MOSI
(Data Output)
for details.
Mode Min.
Master
Master
Master
Master
Master
Master
Master
Master
Slave
Slave 4 • t
(1)
Slave 2 • t
Slave
Slave
Slave
Slave
Slave
Slave
Slave 2 • t
6
4 5
MSB
7
MSB
Typ.
See Table 64
50% duty cycle
3.6
10
10
0.5 • t
sck
10
10
15
ck
ck
10
t
ck
15
20
10
ck
1
2
... LSB
... LSB
Max.
ns
1.6
2
3
8
4317I–AVR–01/08