Table of Contents
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Features
•
Incorporates the ARM7TDMI
- High-performance 32-bit RISC Architecture
- High-density 16-bit Instruction Set
- Leader in MIPS/Watt
- Embedded ICE In-circuit Emulation, Debug Communication Channel Support
•
Internal High-speed Flash
- 256 Kbytes (AT91SAM7XC256) Organized in 1024 Pages of 256 Bytes
- 128 Kbytes (AT91SAM7XC128) Organized in 512 Pages of 256 Bytes
- Single Cycle Access at Up to 30 MHz in Worst Case Conditions
- Prefetch Buffer Optimizing Thumb Instruction Execution at Maximum Speed
Sector Lock Capabilities, Flash Security Bit
- Fast Flash Programming Interface for High Volume Production
•
Internal High-speed SRAM, Single-cycle Access at Maximum Speed
•
- Embedded Flash Controller, Abort Status and Misalignment Detection
•
- Based on Power-on Reset Cells and Low-power Factory-calibrated Brownout
Detector
- Provides External Reset Signal Shaping and Reset Source Status
•
- Low-power RC Oscillator, 3 to 20 MHz On-chip Oscillator and one PLL
•
- Power Optimization Capabilities, Including Slow Clock Mode (Down to 500 Hz) and
- Four Programmable External Clock Signals
•
- Individually Maskable, Eight-level Priority, Vectored Interrupt Sources
- Two External Interrupt Sources and One Fast Interrupt Source, Spurious Interrupt
Protected
•
- 2-wire UART and Support for Debug Communication Channel interrupt,
Programmable ICE Access Prevention
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Periodic Interval Timer (PIT)
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Windowed Watchdog (WDT)
- Counter May Be Stopped While the Processor is in Debug State or in Idle Mode
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- Runs Off the Internal RC Oscillator
•
Two Parallel Input/Output Controllers (PIO)
- Sixty-two Programmable I/O Lines Multiplexed with up to Two Peripheral I/Os
- Input Change Interrupt Capability on Each I/O Line
- Individually Programmable Open-drain, Pull-up Resistor and Synchronous Output
®
®
®
Processor
AT91 ARM
Thumb
Microcontrollers
AT91SAM7XC256
AT91SAM7XC128
Summary
Preliminary
Note: This is a summary document. A complete document
is available on our Web site at www.atmel.com.
®
®
-based
6209AS-ATARM-20-Oct-05
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Table of Contents
Related Manuals for Atmel AT91 Series
Summary of Contents for Atmel AT91 Series
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Page 1: Table Of Contents
– Sixty-two Programmable I/O Lines Multiplexed with up to Two Peripheral I/Os – Input Change Interrupt Capability on Each I/O Line 6209AS–ATARM–20-Oct-05 – Individually Programmable Open-drain, Pull-up Resistor and Synchronous Output Note: This is a summary document. A complete document is available on our Web site at www.atmel.com. - Page 2 – Double PWM Generation, Capture/Waveform Mode, Up/Down Capability • One Four-channel 16-bit Power Width Modulation Controller (PWMC) • One Two-wire Interface (TWI) – Master Mode Support Only, All Two-wire Atmel EEPROMs Supported • One 8-channel 10-bit Analog-to-Digital Converter, Four Channels Multiplexed with Digital I/Os ™ •...
- Page 3 AT91SAM7XC256/128 Preliminary 1. Description Atmel's AT91SAM7XC256/128 is a member of a series of highly integrated Flash microcontrol- lers based on the 32-bit ARM RISC processor. It features 256/128 Kbyte high-speed Flash and 64/32 Kbyte SRAM, a large set of peripherals, including an 802.3 Ethernet MAC, a CAN control- ler, an AES 128 Encryption accelerator and a Triple Data Encryption System.
- Page 4 3. AT91SAM7XC256/128 Block Diagram Figure 3-1. AT91SAM7XC256/128 Block Diagram ARM7TDMI JTAG SCAN Processor JTAGSEL 1.8 V VDDIN Voltage System Controller Regulator VDDOUT VDDCORE VDDIO IRQ0-IRQ1 Memory Controller SRAM Embedded Address 64/32 Kbytes Flash DRXD Decoder DBGU Controller DTXD Abort Misalignment PCK0-PCK3 Status Detection...
- Page 5 AT91SAM7XC256/128 Preliminary 4. Signal Description Table 4-1. Signal Description List Active Signal Name Function Type Level Comments Power Voltage Regulator and ADC Power VDDIN Power 3V to 3.6V Supply Input VDDOUT Voltage Regulator Output Power 1.85V VDDFLASH Flash and USB Power Supply Power 3V to 3.6V VDDIO...
- Page 6 Table 4-1. Signal Description List (Continued) Active Signal Name Function Type Level Comments USB Device Port USB Device Port Data - Analog USB Device Port Data + Analog USART SCK0 - SCK1 Serial Clock TXD0 - TXD1 Transmit Data RXD0 - RXD1 Receive Data Input RTS0 - RTS1...
- Page 7 AT91SAM7XC256/128 Preliminary Table 4-1. Signal Description List (Continued) Active Signal Name Function Type Level Comments Analog-to-Digital Converter AD0-AD3 Analog Inputs Analog Digital pulled-up inputs at reset AD4-AD7 Analog Inputs Analog Analog Inputs ADTRG ADC Trigger Input ADVREF ADC Reference Analog Fast Flash Programming Interface PGMEN0-PGMEN1 Programming Enabling...
- Page 8 5. Package The AT91SAM7XC256/128 is available in 100-lead LQFP package. 100-lead LQFP Mechanical Overview Figure 5-1 shows the orientation of the 100-lead LQFP package. A detailed mechanical descrip- tion is given in the Mechanical Characteristics section of the full datasheet. Figure 5-1.
- Page 9 AT91SAM7XC256/128 Preliminary 6. Power Considerations Power Supplies The AT91SAM7XC256/128 has six types of power supply pins and integrates a voltage regula- tor, allowing the device to be supplied with only one voltage. The six power supply pin types are: • VDDIN pin. It powers the voltage regulator and the ADC; voltage ranges from 3.0V to 3.6V, 3.3V nominal.
- Page 10 Adequate input supply decoupling is mandatory for VDDIN in order to improve startup stability and reduce source voltage drop. The input decoupling capacitor should be placed close to the chip. For example, two capacitors can be used in parallel: 100 nF NPO and 4.7 µF X7R. Typical Powering Schematics The AT91SAM7XC256/128 supports a 3.3V single supply mode.
- Page 11 AT91SAM7XC256/128 Preliminary 7. I/O Lines Considerations JTAG Port Pins TMS, TDI and TCK are schmitt trigger inputs and are not 5-V tolerant. TMS, TDI and TCK do not integrate a pull-up resistor. TDO is an output, driven at up to VDDIO, and has no pull-up resistor. The JTAGSEL pin is used to select the JTAG boundary scan when asserted at a high level.
- Page 12 I/O Lines Current Drawing The PIO lines PA0 to PA3 are high-drive current capable. Each of these I/O lines can drive up to 16 mA permanently. The remaining I/O lines can draw only 8 mA. However, the total current drawn by all the I/O lines cannot exceed 200 mA. AT91SAM7XC256/128 Preliminary 6209AS–ATARM–20-Oct-05...
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Page 13: Arm
AT91SAM7XC256/128 Preliminary 8. Processor and Architecture ARM7TDMI Processor • RISC processor based on ARMv4T Von Neumann architecture – Runs at up to 55 MHz, providing 0.9 MIPS/MHz • Two instruction sets ® – ARM high-performance 32-bit instruction set ® – Thumb high code density 16-bit instruction set •... - Page 14 • Embedded Flash Controller – Embedded Flash interface, up to three programmable wait states – Prefetch buffer, buffering and anticipating the 16-bit requests, reducing the required wait states – Key-protected program, erase and lock/unlock sequencer – Single command for erasing, programming and locking operations –...
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Page 15: Page Programming Time: 6 Ms, Including Page Auto-Erase
AT91SAM7XC256/128 Preliminary 9. Memory AT91SAM7XC256 • 256 Kbytes of Flash Memory – 1024 pages of 256 bytes – Fast access time, 30 MHz single-cycle access in Worst Case conditions – Page programming time: 6 ms, including page auto-erase – Page programming without auto-erase: 3 ms –... - Page 16 Memory Mapping 9.3.1 Internal RAM • The AT91SAM7XC256 embeds a high-speed 64-Kbyte SRAM bank • The AT91SAM7XC128 embeds a high-speed 32-Kbyte SRAM bank. After reset and until the Remap Command is performed, the SRAM is only accessible at address 0x0020 0000. After Remap, the SRAM also becomes available at address 0x0. 9.3.2 Internal ROM The AT91SAM7XC256/128 embeds an Internal ROM.
- Page 17 AT91SAM7XC256/128 Preliminary Figure 9-2. Internal Memory Mapping with GPNVM Bit 2 = 1 0x0000 0000 Flash Before Remap 1 M Bytes SRAM After Remap 0x000F FFFF 0x0010 0000 Internal FLASH 1 M Bytes 0x001F FFFF 0x0020 0000 Internal SRAM 256M Bytes 1 M Bytes 0x002F FFFF 0x0030 0000...
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Page 18: Kbytes (At91Sam7Xc256)
9.4.3 Lock Regions 9.4.3.1 AT91SAM7XC256 The Embedded Flash Controller manages 16 lock bits to protect 16 regions of the flash against inadvertent flash erasing or programming commands. The AT91SAM7XC256 contains 16 lock regions and each lock region contains 64 pages of 256 bytes. Each lock region has a size of 16 Kbytes. - Page 19 AT91SAM7XC256/128 Preliminary • GPNVM Bit 0 is used as a brownout detector enable bit. Setting the GPNVM Bit 0 enables the BOD, clearing it disables the BOD. Asserting ERASE clears the GPNVM Bit 0 and thus disables the brownout detector by default. •...
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Page 20: Memory Controller (Mc)
10. System Controller The System Controller manages all vital blocks of the microcontroller: interrupts, clocks, power, time, debug and reset. Figure 10-1. System Controller Block Diagram Boundary Scan System Controller jtag_nreset TAP Controller nirq irq0-irq1 Advanced nfiq Interrupt proc_nreset ARM7TDMI Controller periph_irq[2..19] debug... - Page 21 AT91SAM7XC256/128 Preliminary 10.1 System Controller Mapping The System Controller peripherals are all mapped to the highest 4 Kbytes of address space, between addresses 0xFFFF F000 and 0xFFFF FFFF. Figure 10-2 shows the mapping of the System Controller. Note that the Memory Controller con- figuration user interface is also mapped within this address space.
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Page 22: Reset Controller (Rstc)
10.2 Reset Controller • Based on one power-on reset cell and one brownout detector • Status of the last reset, either Power-up Reset, Software Reset, User Reset, Watchdog Reset, Brownout Reset • Controls the internal resets and the NRST pin output •... -
Page 23: Clock Generator (Ckgr)
AT91SAM7XC256/128 Preliminary 10.3 Clock Generator The Clock Generator embeds one low-power RC Oscillator, one Main Oscillator and one PLL with the following characteristics: • RC Oscillator ranges between 22 KHz and 42 KHz • Main Oscillator frequency ranges between 3 and 20 MHz •... -
Page 24: Power Management Controller (Pmc)
10.4 Power Management Controller The Power Management Controller uses the Clock Generator outputs to provide: • the Processor Clock PCK • the Master Clock MCK • the USB Clock UDPCK • all the peripheral clocks, independently controllable • four programmable clock outputs The Master Clock (MCK) is programmable from a few hundred Hz to the maximum operating fre- quency of the device. -
Page 25: Debug Unit (Dbgu)
AT91SAM7XC256/128 Preliminary – Higher priority interrupts can be served during service of lower priority interrupt • Vectoring – Optimizes interrupt service routine branch and execution – One 32-bit vector register per interrupt source – Interrupt vector register reads the corresponding current interrupt vector •... - Page 26 10.10 PIO Controllers • Two PIO Controllers, each controlling 31 I/O lines • Fully programmable through set/clear registers • Multiplexing of two peripheral functions per I/O line • For each I/O line (whether assigned to a peripheral or used as general-purpose I/O) –...
- Page 27 AT91SAM7XC256/128 Preliminary 11. Peripherals 11.1 Peripheral Mapping Each peripheral is allocated 16 Kbytes of address space. Figure 11-1. User Peripheral Mapping Peripheral Name 0xF000 0000 Size Reserved 0xFFF9 FFFF 0xFFFA 0000 TC0, TC1, TC2 Timer/Counter 0, 1 and 2 16 Kbytes 0xFFFA 3FFF 0xFFFA 4000 Advanced Encryption Standard...
- Page 28 11.2 Peripheral Multiplexing on PIO Lines The AT91SAM7XC256/128 features two PIO controllers, PIOA and PIOB, that multiplex the I/O lines of the peripheral set. Each PIO Controller controls 31 lines. Each line can be assigned to one of two peripheral func- tions, A or B.
- Page 29 AT91SAM7XC256/128 Preliminary 11.3 PIO Controller A Multiplexing Table 11-1. Multiplexing on PIO Controller A PIO Controller A Application Usage I/O Line Peripheral A Peripheral B Comments Function Comments RXD0 High-Drive TXD0 High-Drive SCK0 SPI1_NPCS1 High-Drive RTS0 SPI1_NPCS2 High-Drive CTS0 SPI1_NPCS3 RXD1 TXD1 SCK1...
- Page 30 11.4 PIO Controller B Multiplexing Table 11-2. Multiplexing on PIO Controller B PIO Controller A Application Usage I/O Line Peripheral A Peripheral B Comments Function Comments ETXCK/EREFCK PCK0 ETXEN ETX0 ETX1 ECRS ERX0 ERX1 ERXER EMDC EMDIO PB10 ETX2 SPI1_NPCS1 PB11 ETX3 SPI1_NPCS2...
- Page 31 AT91SAM7XC256/128 Preliminary 11.5 Peripheral Identifiers The AT91SAM7XC256/128 embeds a wide range of peripherals. Table 11-3 defines the Periph- eral Identifiers of the AT91SAM7XC256/128. Unique peripheral identifiers are defined for both the Advanced Interrupt Controller and the Power Management Controller. Table 11-3. Peripheral Identifiers External Peripheral ID...
- Page 32 11.6 Ethernet MAC • DMA Master on Receive and Transmit Channels • Compatible with IEEE Standard 802.3 • 10 and 100 Mbit/s operation • Full- and half-duplex operation • Statistics Counter Registers • MII/RMII interface to the physical layer • Interrupt generation to signal receive and transmit completion •...
- Page 33 AT91SAM7XC256/128 Preliminary • One, two or three bytes for slave address • Sequential read/write operations 11.9 USART • Programmable Baud Rate Generator • 5- to 9-bit full-duplex synchronous or asynchronous serial communications – 1, 1.5 or 2 stop bits in Asynchronous Mode –...
- Page 34 – Delay timing – Pulse Width Modulation – Up/down capabilities • Each channel is user-configurable and contains: – Three external clock inputs • Five internal clock inputs, as defined in Table 11-4 Table 11-4. Timer Counter Clocks Assignment TC Clock input Clock TIMER_CLOCK1 MCK/2...
- Page 35 AT91SAM7XC256/128 Preliminary 11.14 CAN Controller • Fully compliant with CAN 2.0A and 2.0B • Bit rates up to 1Mbit/s • Eight object oriented mailboxes each with the following properties: – CAN Specification 2.0 Part A or 2.0 Part B Programmable for each Message –...
- Page 36 • 18-clock Cycles Encryption/Decryption Processing Time for DES • 50-clock Cycles Encryption/Decryption Processing Time for TDES • Support the Four Standard Modes of Operation specified in the FIPS Publication 81, DES • Modes of Operation: – Electronic Codebook (ECB) – Cipher Block Chaining (CBC) –...
- Page 37 AT91SAM7XC256/128 Preliminary 12. AT91SAM7XC256/128 Ordering Information Table 12-1. Ordering Information Temperature Ordering Code Package Package Type Operating Range Industrial AT91SAM7XC256-AU LQFP 100 Green (-40° C to 85° C) Industrial AT91SAM7XC128-AU LQFP 100 Green (-40° C to 85° C) 13. Export Regulations Statement These commodities, technology or software will be exported from France and the applicable Export Administration Regulations will apply.
- Page 38 Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI- TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY...