Atmel AT90PWM2 Manual page 293

25.9 Serial Downloading
AT90PWM2/3/2B/3B
294
Table 25-14. Parallel Programming Characteristics, V
Symbol Parameter
t XTAL1 Low to PAGEL high
XLPH
t PAGEL low to XTAL1 high
PLXH
t BS1 Valid before PAGEL High
BVPH
t PAGEL Pulse Width High
PHPL
t BS1 Hold after PAGEL Low
PLBX
t BS2/1 Hold after WR Low
WLBX
t PAGEL Low to WR Low
PLWL
t BS1 Valid to WR Low
BVWL
t WR Pulse Width Low
WLWH
t WR Low to RDY/BSY Low
WLRL
t WR Low to RDY/BSY High
WLRH
t WR Low to RDY/BSY High for Chip Erase
WLRH_CE
t XTAL1 Low to OE Low
XLOL
t BS1 Valid to DATA valid
BVDV
t OE Low to DATA Valid
OLDV
t OE High to DATA Tri-stated
OHDZ
Notes: 1. t is valid for the Write Flash, Write EEPROM, Write Fuse bits and Write Lock bits
WLRH
commands.
2. t is valid for the Chip Erase command.
WLRH_CE
Both the Flash and EEPROM memory arrays can be programmed using the serial SPI bus while
RESET is pulled to GND. The serial interface consists of pins SCK, MOSI (input) and MISO (out-
put). After RESET is set low, the Programming Enable instruction needs to be executed first
before program/erase operations can be executed. NOTE, in
mapping for SPI programming is listed. Not all parts use the SPI pins dedicated for the internal
SPI interface.
= 5V ± 10% (Continued)
CC
(1)
(2)
Table 25-13 on page
Min Typ Max Units
0
150
67
150
67
67
67
67
150
0 1
3.7 4.5 ms
7.5 9 ms
0
0 250
250
250
285, the pin
4317I–AVR–01/08
ns
ns
ns
ns
ns
ns
ns
ns
ns
μs
ns
ns
ns
ns