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AVR XMEGA D Series
Atmel AVR XMEGA D Series Manuals
Manuals and User Guides for Atmel AVR XMEGA D Series. We have
1
Atmel AVR XMEGA D Series manual available for free PDF download: Manual
Atmel AVR XMEGA D Series Manual (331 pages)
8-bit
Brand:
Atmel
| Category:
Microcontrollers
| Size: 4.4 MB
Table of Contents
1 About the Manual
2
Reading the Manual
2
Resources
2
Recommended Reading
2
2 Overview
3
Block Diagram
4
3 Avr Cpu
5
Features
5
Overview
5
Architectural Overview
5
ALU - Arithmetic Logic Unit
6
Program Flow
7
Instruction Execution Timing
7
Status Register
8
Stack and Stack Pointer
8
Register File
9
RAMP and Extended Indirect Registers
10
Accessing 16-Bit Registers
11
Configuration Change Protection
11
Fuse Lock
12
Register Descriptions
13
Register Summary
16
4 Memories
17
Features
17
Overview
17
Flash Program Memory
17
Fuses and Lockbits
19
Data Memory
19
Internal SRAM
20
Eeprom
20
I/O Memory
20
Memory Timing
21
Device ID and Revision
21
I/O Memory Protection
21
Register Description - NVM Controller
22
Register Descriptions - Fuses and Lockbits
27
Register Description - Production Signature Row
33
Register Description - General Purpose I/O Memory
39
Register Descriptions - MCU Control
39
Register Summary - NVM Controller
42
Register Summary - Fuses and Lockits
42
Register Summary - Production Signature Row
43
Register Summary - General Purpose I/O Registers
44
Register Summary - MCU Control
44
Interrupt Vector Summary - NVM Controller
44
5 Event System
45
Features
45
Overview
45
Events
46
Event Routing Network
48
Event Timing
50
Filtering
50
Quadrature Decoder
50
Register Description
53
Register Summary
57
6 System Clock and Clock Options
58
Features
58
Overview
58
Clock Distribution
60
Clock Sources
60
System Clock Selection and Prescalers
62
PLL with 1X-31X Multiplication Factor
63
DFLL 2Mhz and DFLL 32Mhz
64
PLL and External Clock Source Failure Monitor
65
Register Description - Clock
67
Register Description - Oscillator
70
Register Description - DFLL32M/DFLL2M
75
Register Summary - Clock
78
Register Summary - Oscillator
78
Register Summary - DFLL32M/DFLL2M
78
Oscillator Failure Interrupt Vector Summary
78
7 Power Management and Sleep Modes
79
Features
79
Overview
79
Sleep Modes
79
Power Reduction Registers
81
Minimizing Power Consumption
81
Register Description - Sleep
83
Register Description - Power Reduction
83
Register Summary - Sleep
86
Register Summary - Power Reduction
86
8 Reset System
87
Features
87
Overview
87
Reset Sequence
88
Reset Sources
89
Register Description
93
Register Summary
94
9 WDT - Watchdog Timer
95
Features
95
Overview
95
Normal Mode Operation
95
Window Mode Operation
96
Watchdog Timer Clock
96
Configuration Protection and Lock
97
Registers Description
97
Register Summary
100
10 Interrupts and Programmable Multilevel Interrupt Controller
101
Features
101
Overview
101
Operation
102
Interrupts
102
Interrupt Level
105
Interrupt Priority
105
Interrupt Vector Locations
107
Register Description
107
Register Summary
109
11 O Ports
110
Features
110
Overview
110
I/O Pin Use and Configuration
111
Reading the Pin Value
114
Input Sense Configuration
115
Port Interrupt
116
Port Event
117
Alternate Port Functions
117
Slew Rate Control
118
Clock and Event Output
118
Multi-Pin Configuration
119
Virtual Ports
119
Register Descriptions - Ports
120
Register Descriptions - Port Configuration
126
Register Descriptions - Virtual Port
130
Register Summary - Ports
132
Register Summary - Port Configuration
132
Register Summary - Virtual Ports
132
Interrupt Vector Summary - Ports
133
12 TC0/1 - 16-Bit Timer/Counter Type 0 and 1
134
Features
134
Overview
134
Block Diagram
136
Clock and Event Sources
137
Double Buffering
137
Counter Operation
138
Capture Channel
140
Compare Channel
143
Interrupts and Events
147
Timer/Counter Commands
147
Register Description
148
Register Summary
158
Interrupt Vector Summary
158
13 Hi-Res - High-Resolution Extension
159
Features
159
Overview
159
Register Description
160
Register Summary
160
14 Awex - Advanced Waveform Extension
161
Features
161
Overview
161
Port Override
162
Dead-Time Insertion
163
Pattern Generation
164
Fault Protection
165
Register Description
167
Register Summary
171
15 RTC - Real-Time Counter
172
Features
172
Overview
172
Register Descriptions
174
Register Summary
179
Interrupt Vector Summary
179
16 TWI - Two-Wire Interface
180
Features
180
Overview
180
General TWI Bus Concepts
181
TWI Bus State Logic
186
TWI Master Operation
187
TWI Slave Operation
189
Enabling External Driver Interface
191
Register Description - TWI
192
Register Description - TWI Master
193
Register Description - TWI Slave
198
Register Summary - TWI
204
Register Summary - TWI Master
204
Register Summary - TWI Slave
204
Interrupt Vector Summary
204
17 SPI - Serial Peripheral Interface
205
Features
205
Overview
205
Master Mode
206
Slave Mode
206
Data Modes
207
Register Description
208
Register Summary
211
Interrupt Vector Summary
211
18 Usart
212
Features
212
Overview
212
Clock Generation
214
Frame Formats
217
USART Initialization
218
Data Transmission - the USART Transmitter
218
Data Reception - the USART Receiver
219
Asynchronous Data Reception
220
Fractional Baud Rate Generation
223
USART in Master SPI Mode
224
USART SPI Vs. SPI
224
Multiprocessor Communication Mode
225
IRCOM Mode of Operation
225
Register Description
227
Register Summary
233
Interrupt Vector Summary
233
19 IRCOM - IR Communication Module
234
Features
234
Overview
234
Registers Description
236
Register Summary
237
20 CRC - Cyclic Redundancy Check
238
Features
238
Overview
238
Operation
239
CRC on Flash Memory
239
CRC Using the I/O Interface
240
Register Description
241
Register Sumary
244
21 ADC - Analog-To-Digital Converter
245
Features
245
Overview
245
Input Sources
246
Sampling Time Control
249
Voltage Reference Selection
249
Conversion Result
250
Compare Function
251
Starting a Conversion
252
ADC Clock and Conversion Timing
252
ADC Input Model
255
Interrupts and Events
256
Calibration
256
Synchronous Sampling
256
Register Description - ADC
257
Register Description - ADC Channel
264
Register Summary - ADC
270
Register Summary - ADC Channel
270
Interrupt Vector Summary
270
22 AC - Analog Comparator
271
Features
271
Overview
271
Input Sources
272
Signal Compare
272
Interrupts and Events
272
Window Mode
273
Input Hysteresis
273
Register Description
274
Register Summary
280
Interrupt Vector Summary
280
23 Program and Debug Interface
281
Features
281
Overview
281
PDI Physical
282
PDI Controller
286
Register Description - PDI Instruction and Addressing Registers
290
Register Description - PDI Control and Status Registers
292
Register Summary
293
24 Memory Programming
294
Features
294
Overview
294
NVM Controller
295
NVM Commands
295
NVM Controller Busy Status
295
Flash and EEPROM Page Buffers
296
Flash and EEPROM Programming Sequences
297
Protection of NVM
298
Preventing NVM Corruption
298
CRC Functionality
298
Self-Programming and Boot Loader Support
298
External Programming
309
Register Description
315
Register Summary
315
25 Peripheral Module Address Map
316
26 Instruction Set Summary
317
27 Datasheet Revision History
321
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