Atmel AT90PWM2 Manual page 163

8-bit avr microcontroller with 8k bytes in-system programmable flash
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16.25.7
Output Compare RB Register – OCRnRBH and OCRnRBL
16.25.8
PSC 0 Configuration Register – PCNF0
16.25.9
PSC 1 Configuration Register – PCNF1
16.25.10 PSC 2 Configuration Register – PCNF2
AT90PWM2/3/2B/3B
164
Read/Write
W
Initial Value
0
Bit
7
Read/Write
W
Initial Value
0
Note : n = 0 to 2 according to PSC number.
The Output Compare Registers RA, RB, SA and SB contain a 12-bit value that is continuously
compared with the PSC counter value. A match can be used to generate an Output Compare
interrupt, or to generate a waveform output on the associated pin.
The Output Compare Registers RB contains also a 4-bit value that is used for the flank width
modulation.
The Output Compare Registers are 16bit and 12-bit in size. To ensure that both the high and low
bytes are written simultaneously when the CPU writes to these registers, the access is per-
formed using an 8-bit temporary high byte register (TEMP). This temporary register is shared by
all the other 16-bit registers.
Bit
7
PFIFTY0
PALOCK0
Read/Write
R/W
Initial Value
0
Bit
7
PFIFTY1
PALOCK1
Read/Write
R/W
Initial Value
0
Bit
7
PFIFTY2
PALOCK2
Read/Write
R/W
Initial Value
0
The PSC n Configuration Register is used to configure the running mode of the PSC.
• Bit 7 - PFIFTYn: PSC n Fifty
Writing this bit to one, set the PSC in a fifty percent mode where only OCRnRBH/L and
OCRnSBH/L are used. They are duplicated in OCRnRAH/L and OCRnSAH/L during the update
of OCRnRBH/L. This feature is useful to perform fifty percent waveforms.
• Bit 6 - PALOCKn: PSC n Autolock
When this bit is set, the Output Compare Registers RA, SA, SB, the Output Matrix POM2 and
the PSC Output Configuration PSOCn can be written without disturbing the PSC cycles. The
W
W
W
0
0
0
6
5
4
OCRnRB[15:12]
OCRnRB[7:0]
W
W
W
0
0
0
6
5
4
PLOCK0
PMODE01
R/W
R/W
R/W
0
0
0
6
5
4
PLOCK1
PMODE11
R/W
R/W
R/W
0
0
0
6
5
4
PLOCK2
PMODE21
R/W
R/W
R/W
0
0
0
W
W
W
0
0
0
3
2
1
OCRnRB[11:8]
W
W
W
0
0
0
3
2
1
PMODE00
POP0
PCLKSEL0
R/W
R/W
R/W
0
0
0
3
2
1
PMODE10
POP1
PCLKSEL1
R/W
R/W
R/W
0
0
0
3
2
1
PMODE20
POP2
PCLKSEL2
R/W
R/W
R/W
0
0
0
W
0
0
OCRnRBH
OCRnRBL
W
0
0
-
PCNF0
R/W
0
0
-
PCNF1
R/W
0
0
POME2
PCNF2
R/W
0
4317I–AVR–01/08

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